AES Encryption Algorithm Hardware Implementation Architecture: Resource and Execution Time Optimization

2012 ◽  
Vol 1 (2) ◽  
Author(s):  
Samir El Adib ◽  
Naoufal Raissouni
Keyword(s):  
Execution Time ◽  
Hardware Implementation ◽  
Encryption Algorithm ◽  
Time Optimization ◽  
Aes Encryption Algorithm

AES Encryption Algorithm Hardware Implementation: Throughput and Area Comparison of 128, 192 and 256-bits Key

2012 ◽  
Vol 1 (2) ◽  
pp. 67 ◽  
Author(s):  
Samir El Adib ◽  
Naoufal Raissouni
Keyword(s):  
Hardware Implementation ◽  
Data Encryption ◽  
Encryption Algorithm ◽  
Advanced Encryption Standard ◽  
Data Encryption Standard ◽  
Security Applications ◽  
High Security ◽  
Aes Encryption Algorithm ◽  
Existing Data

<span lang="EN-US">Advanced Encryption Standard (AES) adopted by the National Institute of Standards and Technology (NIST) to replace existing Data Encryption Standard (DES), as the most widely used encryption algorithm in many security applications. Up to today, AES standard has key size variants of 128, 192, and 256-bit, where longer bit keys provide more secure ciphered text output. In the hardware perspective, bigger key size also means bigger area and small throughput. Some companies that employ ultra-high security in their systems may look for a key size bigger than 128-bit AES. In this paper, 128, 192 and 256-bit AES hardware are implemented and compared in terms of throughput and area. The target hardware used in this paper is Virtex XC5VLX50 FPGA from Xilinx. Total area and Throughput results are presented and graphically compared.</span>

scholarly journals Iris Matching Step Implementation in FPGA

2019 ◽  
Vol 2 (1) ◽  
pp. 26-36
Author(s):  
Aumama M. Farhan ◽  
M. F. Al-Gailani
Keyword(s):  
Execution Time ◽  
Iris Recognition ◽  
Hardware Implementation ◽  
Hamming Distance ◽  
Computation Time ◽  
Recognition System ◽  
Hardware Platform ◽  
System Generator ◽  
Large Memory ◽  
Powerful Strategy

Iris recognition system is broadly being utilized as it has distinctive patterns that gives it a powerful strategy to distinguish between persons for identification purposes. However, this system in this implementation requires large memory capacity and high computation time. These factors make us in a challenge to find a way to run this algorithm in a hardware platform. The hardware implementation features reduce the execution time by exploiting the parallelism and pipeline. The present work addresses this issue when reducing execution time by implementing the matching step using hamming distance algorithm on the target device FPGA KINTEX 7 using Xilinx system generator. The obtained result demonstrates that the execution time has been accelerated to 1.32 ns, which is almost at least four times faster than existing works

Recent Advances Delivered in Mobile Cloud Computing's Security and Management Challenges

2020 ◽  
pp. 21-43
Author(s):  
Christos Stergiou ◽  
Kostas E. Psannis
Keyword(s):  
Cloud Computing ◽  
Mobile Device ◽  
Mobile Cloud Computing ◽  
New Method ◽  
Encryption Algorithm ◽  
Mobile Cloud ◽  
Cloud Environment ◽  
Computational Power ◽  
Access To Data ◽  
Aes Encryption Algorithm

Mobile cloud computing provides an opportunity to restrict the usage of huge hardware infrastructure and to provide access to data, applications, and computational power from every place and in any time with the use of a mobile device. Furthermore, MCC offers a number of possibilities but additionally creates several challenges and issues that need to be addressed as well. Through this work, the authors try to define the most important issues and challenges in the field of MCC technology by illustrating the most significant works related to MCC during recent years. Regarding the huge benefits offered by the MCC technology, the authors try to achieve a more safe and trusted environment for MCC users in order to operate the functions and transfer, edit, and manage data and applications, proposing a new method based on the existing AES encryption algorithm, which is, according to the study, the most relevant encryption algorithm to a cloud environment. Concluding, the authors suggest as a future plan to focus on finding new ways to achieve a better integration MCC with other technologies.

ViPar: High-Level Design Space Exploration for Parallel Video Processing Architectures

2019 ◽  
Vol 2019 ◽  
pp. 1-19
Author(s):  
Karim M. A. Ali ◽  
Rabie Ben Atitallah ◽  
Abdessamad Ait El Cadi ◽  
Nizar Fakhfakh ◽  
Jean-Luc Dekeyser
Keyword(s):  
Power Consumption ◽  
Video Processing ◽  
Execution Time ◽  
Design Space Exploration ◽  
Hardware Implementation ◽  
Space Exploration ◽  
Absolute Difference ◽  
Architectural Model ◽  
Processing Architectures ◽  
High Level

Embedded video applications are now involved in sophisticated transportation systems like autonomous vehicles and driver assistance systems. As silicon capacity increases, the design productivity gap grows up for the current available design tools. Hence, high-level synthesis (HLS) tools emerged in order to reduce that gap by shifting the design efforts to higher abstraction levels. In this paper, we present ViPar as a tool for exploring different video processing architectures at higher design level. First, we proposed a parametrizable parallel architectural model dedicated for video applications. Second, targeting this architectural model, we developed ViPar tool with two main features: (1) An empirical model was introduced to estimate the power consumption based on hardware utilization and operating frequency. In addition to that, we derived the equations for estimating the hardware utilization and execution time for each design point during the space exploration process. (2) By defining the main characteristics of the parallel video architecture like parallelism level, the number of input/output ports, the pixel distribution pattern, and so on, ViPar tool can automatically generate the dedicated architecture for hardware implementation. In the experimental validation, we used ViPar tool to generate automatically an efficient hardware implementation for a Multiwindow Sum of Absolute Difference stereo matching algorithm on Xilinx Zynq ZC706 board. We succeeded to increase the design productivity by converging rapidly to the appropriate designs that fit with our system constraints in terms of power consumption, hardware utilization, and frame execution time.

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