Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

This paper introduces a modified multilevel inverter topology with asymmetrical dc sources combination. The significant features of the proposed circuit are the reduced number of switches and low total standing voltage (TSV). Proposed topology utilizes ten switches to produce 13 level output with per unit TSVp.u of 5.33. An additional feature of the proposed topology is the inherent negative level generation as there is no requirement of an H-bridge for the polarity reversals. Nearest level control (NLC) technique is used as the modulation strategy. Performance of the proposed topology is validated through extensive analysis using Simulink and PLECS software. Detailed circuit analysis and its power loss, as well as efficiency studies, have been carried out under constant and dynamic load conditions. Results obtained shows that the proposed topology is working well, producing an output of 13-level with total harmonic distortion of 6.36% and inverter efficiency of 98.8%. The topology is extended to n-level structure, and its generalized expressions for different parameters were formulated. The comparison of the generalized structure with other existing topology is carried out, and it is found that the proposed topology outperform other topologies on many parameters.

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Minimize of Harmonic Distortion and Power Quality Analisis using a New Discontinuous Svpwm of Multilevel Inverer for Indestrial Deives

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.c5894.118419 ◽

2019 ◽

Vol 8 (4) ◽

pp. 8525-8529

Keyword(s):

Pulse Width Modulation ◽

Control Strategies ◽

Harmonic Distortion ◽

Electrical Drive ◽

Power Semiconductor ◽

Medium Voltage ◽

Capacitor Voltage ◽

Semiconductor Switch ◽

High Control ◽

Inverter Topology

The paper proposed space vector pulse width modulation is comparing the author Ramakrishna maheswari and Joan Nicolas reference in the paper. In speed control strategies for the recruitment engine has driven their use in nearly every single electrical drive. For better execution the high control acceptance machines are planned at medium voltage (mv) rating. In the event that single power semiconductor switch is legitimately associated with medium voltage, it might harm. Too, customary inverters produce high recurrence normal mode voltage. Staggered inverter is an elective answer for high control and medium voltage A.C. drive. It begins from three levels. The staggered inverter topology blends a sinusoidal voltage from a few degrees of voltages got from capacitor voltage sources. In this paper, a way to deal with diminish total harmonic distortion utilizing four level diode clamped staggered inverter (DCMLI) for three stage enlistment engine drive is proposed.

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Investigation and Reliability Analysis of Fifteen Level Asymmetrical Multilevel Inverter Topology using Nearest Level Control Technique with low Component Count

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096513999201020213639 ◽

2020 ◽

Vol 13 ◽

Author(s):

Abeera Dutt Roy ◽

Chandrahasan Umayal

Keyword(s):

Reliability Analysis ◽

Electronic Devices ◽

Harmonic Distortion ◽

Multilevel Inverter ◽

Control Technique ◽

Level Control ◽

Multilevel Inverters ◽

Different Types ◽

Performance Abilities ◽

Inverter Topology

Background:: In multilevel inverters (MLI) as the number of level increases, there is a proportionate increase in the count of the semiconductor devices that are employed. Methods:: An asymmetrical multilevel inverter topology using a bidirectional switch is presented which employs lesser number of power electronic devices to produce fifteen levels at the output voltage. Nearest Level modulation (NLM) technique is used to generate the switching pulses and reliability analysis is performed using Markov reliability methodology. The operating principle of the proposed MLI and its performance abilities is verified through MATLAB/Simulink and a prototype is developed to provide the experimental results. Results:: Total Harmonic Distortion (THD) is computed for proposed MLI for different types of loads in simulation environment as well as in the developed hardware prototype. The fifteen level is achieved by using only 9 switches and 3 DC sources in comparison to the 28 switches and 6 DC sources required by the traditional cascaded H-bridge inverter. Conclusion:: The simulation and hardware results confirm the suitability of the proposed fifteen level MLI as the total component count and the requirement of DC sources reduces considerably.

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Asymmetrical multilevel inverter topology with reduced power semiconductor devices

2016 IEEE Industrial Electronics and Applications Conference (IEACon) ◽

10.1109/ieacon.2016.8067349 ◽

2016 ◽

Cited By ~ 5

Author(s):

M. Saad bin Arif ◽

Shahrin Md. Ayob ◽

Zainal Salam

Keyword(s):

Semiconductor Devices ◽

Multilevel Inverter ◽

Power Semiconductor ◽

Power Semiconductor Devices ◽

Inverter Topology

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A New Multilevel Inverter Topology with Reduced DC Sources

Energies ◽

10.3390/en14154709 ◽

2021 ◽

Vol 14 (15) ◽

pp. 4709

Author(s):

Muhyaddin Rawa ◽

Prem P ◽

Jagabar Sathik Mohamed Ali ◽

Marif Daula Siddique ◽

Saad Mekhilef ◽

...

Keyword(s):

Software Tool ◽

Multilevel Inverter ◽

Basic Unit ◽

Peak Efficiency ◽

Power Semiconductor ◽

Power Semiconductor Devices ◽

Higher Power ◽

Control Requirement ◽

The Given ◽

Inverter Topology

The component count for the multilevel inverter has been a research topic for the last few decades. The higher number of power semiconductor devices and sources leads to a higher power loss with the complex control requirement. A new multilevel inverter topology employing the concept of half-Bridge modules is suggested in this paper. It requires a lower number of dc sources and power components. The inverter is controlled using a fundamental frequency switching scheme. With the basic unit being able to produce 13 level voltage waveforms with three dc voltage sources, higher-level inverter configuration has also been discussed in the paper. The performance of the topology is analyzed in the aspects of circuit parameters and found better when compared to similar topologies proposed in recent literature. The comparison provided in the paper set the benchmark of the proposed topology in terms of lower component requirements. The topology is also optimized with two voltage fixing algorithms for maximizing the number of levels for the given number of IGBTs, drivers and dc sources, and the observations are presented. The efficiency analysis gives the peak efficiency as 98.5%. The simulations were carried out using the PLECS software tool and validated using a prototype rated at 500 W. The results with several test conditions have been reported and discussed in the paper.

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Performance Analysis of a Half Bridge Cell Based Asymmetrical Multilevel Inverter Topology with Minimum Components

Recent Advances in Electrical & Electronic Engineering (Formerly Recent Patents on Electrical & Electronic Engineering) ◽

10.2174/2352096512666190417122807 ◽

2020 ◽

Vol 13 (4) ◽

pp. 531-545

Author(s):

Abeera D. Roy ◽

Chandrahasan Umayal

Keyword(s):

Output Voltage ◽

Harmonic Distortion ◽

Multilevel Inverter ◽

Simulation Environment ◽

Level Control ◽

Voltage Waveform ◽

Multilevel Inverters ◽

Different Types ◽

Performance Abilities ◽

Inverter Topology

Background: In Multilevel Inverters (MLI) as the number of level increases, there is a proportionate increase in the count of the semiconductor devices that are employed. Methods: This paper deals with an asymmetrical cascaded H-bridge inverter topology with half bridge cells to produce seven level output voltage waveform. Nearest Level Control (NLM) technique is used to produce the switching pulses. The operating principle of the proposed MLI and its performance abilities is verified through MATLAB/Simulink and a prototype is developed to provide the experimental results. Results: Total Harmonic Distortion (THD) is computed for proposed MLI for different types of loads in simulation environment as well as in the developed hardware prototype. Comparison between the proposed MLI and recent topologies demonstrates the advantageous features. Conclusion: The simulation and hardware results confirm the suitability of the proposed seven level MLI as the total component count, and the requirement of DC sources reduces considerably.

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