Bilinear Interpolation Image Scaling Processor for VLSI Architecure

2014 ◽  
Vol 3 (3) ◽  
pp. 104 ◽  
Author(s):  
Pawar Ashwini Dilip ◽  
K Rameshbabu ◽  
Kanase Prajakta Ashok ◽  
Shital Arjun Shivdas
Keyword(s):  
Vlsi Architecture ◽  
Spatial Filter ◽  
Cmos Process ◽  
Interpolation Algorithm ◽  
Bilinear Interpolation ◽  
Hardware Cost ◽  
Image Scaling ◽  
Memory Buffer ◽  
Convolution Kernels ◽  
Calculation Unit

We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and  a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and  image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCU)is invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 <em>μ</em>m2 synthesized by a 0.13-<em>μ</em>m CMOS process.

Scaling of Engineering Image Based on Interpolation Algorithm

2013 ◽  
Vol 634-638 ◽  
pp. 3989-3993
Author(s):  
Hui Wang ◽  
Guo Jia Li ◽  
Jun Hui Pan
Keyword(s):  
Image Quality ◽  
Experimental Results ◽  
Interpolation Algorithm ◽  
Bilinear Interpolation ◽  
Large Capacity ◽  
Image Scaling

Before the large capacity and engineering image is analyzed carefully, which need to be effective scaled. The subsequent analysis and calculation to engineering image is subjected by image quality and scaling time. According to scaling research of large capacity engineering image, the effect for image scaling by various interpolation algorithm is individual analyzed, and more appropriate algorithm is selected. The experimental results show that the engineering image of best effect is got, when it is high-expansion scaled by double cubic interpolation, and the bilinear interpolation is more suitable for low multiple scaling image.

Video image scaling technology based on adaptive interpolation algorithm and TTS FPGA implementation

2021 ◽  
Vol 76 ◽  
pp. 103516
Author(s):  
Guangyu Liu ◽  
Bao Zhou ◽  
Yi Huang ◽  
Longfei Wang ◽  
Wei Wang ◽  
...  
Keyword(s):  
Fpga Implementation ◽  
Video Image ◽  
Interpolation Algorithm ◽  
Image Scaling ◽  
Adaptive Interpolation

FPGA Implementation of the Bilinear Interpolation Algorithm for Image Demosaicking

2009 ◽  
Author(s):  
Ivan Olaf Hernandez Fuentes ◽  
Miguel Enrique Bravo-Zanoguera ◽  
Guillermo Galaviz Yanez
Keyword(s):  
Fpga Implementation ◽  
Interpolation Algorithm ◽  
Bilinear Interpolation

scholarly journals Simulation of the preparation and face drilling processes with laser scanning and automated marking of the drilling grid

2020 ◽  
Vol 177 ◽  
pp. 01010 ◽  
Author(s):  
Evgeniya Volkova ◽  
Aleksey Druzhinin ◽  
Roman Kuzminykh ◽  
Vladimir Poluzadov
Keyword(s):  
Software Development ◽  
Laser Scanning ◽  
3D Model ◽  
Drilling Process ◽  
Interpolation Algorithm ◽  
Laser Rangefinder ◽  
Bilinear Interpolation ◽  
The Face ◽  
Polygonal Model ◽  
Grid Based

The article discusses the methods of calculating the drilling and blasting scheme and constructing a drilling grid, manual and automatic calculation options are compared. A method for automatically constructing a drilling grid based on laser scanning is proposed. Moreover, the proposed method can be implemented using cheap equipment - a laser rangefinder and an Arduino microcomputer. Based on the data of the laser rangefinder with openCV and SciPy libraries, a polygonal 3D model of the face is built. The transfer of the drilling grid to the 3D model is implemented using the bilinear interpolation algorithm. The constructed polygonal model can be improved by making changes to the construction algorithm, since it is developed by the authors and can be further developed. The simulation model is created in Anylogic software and shows the drilling process taking into account the previously calculated drilling pattern. The proposed models can be used as a basis for further research and software development.

scholarly journals VLSI Implementation of a High-Performance Nonlinear Image Scaling Algorithm

2021 ◽  
Vol 2021 ◽  
pp. 1-10
Author(s):  
Osamah Ibrahim Khalaf ◽  
Carlos Andrés Tavera Romero ◽  
A. Azhagu Jaisudhan Pazhani ◽  
G. Vinuja
Keyword(s):  
High Performance ◽  
Low Cost ◽  
Vlsi Architecture ◽  
Linear Interpolation ◽  
Noisy Environments ◽  
Image Scaling ◽  
Scaling Methods ◽  
Processing Resources ◽  
Weighted Median ◽  
Memory Efficient

This study implements the VLSI architecture for nonlinear-based picture scaling that is minimal in complexity and memory efficient. Image scaling is used to increase or decrease the size of an image in order to map the resolution of different devices, particularly cameras and printers. Larger memory and greater power are also necessary to produce high-resolution photographs. As a result, the goal of this project is to create a memory-efficient low-power image scaling methodology based on the effective weighted median interpolation methodology. Prefiltering is employed in linear interpolation scaling methods to improve the visual quality of the scaled image in noisy environments. By decreasing the blurring effect, the prefilter performs smoothing and sharpening processes to produce high-quality scaled images. Despite the fact that prefiltering requires more processing resources, the suggested solution scales via effective weighted median interpolation, which reduces noise intrinsically. As a result, a low-cost VLSI architecture can be created. The results of simulations reveal that the effective weighted median interpolation outperforms other existing approaches.

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