FPGA Implementation of the Bilinear Interpolation Algorithm for Image Demosaicking

Author(s):  
Ivan Olaf Hernandez Fuentes ◽  
Miguel Enrique Bravo-Zanoguera ◽  
Guillermo Galaviz Yanez
2021 ◽  
Vol 76 ◽  
pp. 103516
Author(s):  
Guangyu Liu ◽  
Bao Zhou ◽  
Yi Huang ◽  
Longfei Wang ◽  
Wei Wang ◽  
...  

2020 ◽  
Vol 177 ◽  
pp. 01010 ◽  
Author(s):  
Evgeniya Volkova ◽  
Aleksey Druzhinin ◽  
Roman Kuzminykh ◽  
Vladimir Poluzadov

The article discusses the methods of calculating the drilling and blasting scheme and constructing a drilling grid, manual and automatic calculation options are compared. A method for automatically constructing a drilling grid based on laser scanning is proposed. Moreover, the proposed method can be implemented using cheap equipment - a laser rangefinder and an Arduino microcomputer. Based on the data of the laser rangefinder with openCV and SciPy libraries, a polygonal 3D model of the face is built. The transfer of the drilling grid to the 3D model is implemented using the bilinear interpolation algorithm. The constructed polygonal model can be improved by making changes to the construction algorithm, since it is developed by the authors and can be further developed. The simulation model is created in Anylogic software and shows the drilling process taking into account the previously calculated drilling pattern. The proposed models can be used as a basis for further research and software development.


Author(s):  
Pawar Ashwini Dilip ◽  
K Rameshbabu ◽  
Kanase Prajakta Ashok ◽  
Shital Arjun Shivdas

We introduce image scaling processor using VLSI technique. It consist of Bilinear interpolation, clamp filter and  a sharpening spatial filter. Bilinear interpolation algorithm is popular due to its computational efficiency and  image quality. But resultant image consist of blurring edges and aliasing artifacts after scaling. To reduce the blurring and aliasing artifacts sharpening spatial filter and clamp filters are used as pre-filter. These filters are realized by using T-model and inversed T-model convolution kernels. To reduce the memory buffer and computing resources for proposed image processor design two T-model or inversed T-model filters are combined into combined filter which requires only one line buffer memory. Also, to reduce hardware cost Reconfigurable calculation unit (RCU)is invented. The VLSI architecture in this work can achieve 280 MHz with 6.08-K gate counts, and its core area is 30 378 <em>μ</em>m2 synthesized by a 0.13-<em>μ</em>m CMOS process.


2012 ◽  
Vol 461 ◽  
pp. 206-210 ◽  
Author(s):  
Zhi Gang Li ◽  
Yu Qian Zhao

Low contrast and shortage of gray levels are two main characteristics of infrared image. According to the characteristics of infrared image, a simple and practical video format MHIVF (Mitthögskolans Interlaced Video Format) and conversion technique are introduced. This kind of video format can simplify the infrared image processing. Infrared image real-time enlargement system based on FPGA is designed and the bilinear interpolation algorithm is selected for image enlargement. The experiment results show that the designed system has a lower complexity and image processing speed is obviously increased


2014 ◽  
Vol 513-517 ◽  
pp. 3773-3776 ◽  
Author(s):  
Wei Guo ◽  
Chuan Zhang ◽  
Yong Rui Zheng

This paper brings about an image distortion correction system based on FPGA with low latency and high quality. In line with image format characteristics, the system adopted the buffering mechanism that storing data in odd and even line/column zones respectively to minimize memory occupancy. Furthermore, an improved bilinear interpolation algorithm is put forward in order to improve edge definition. The experiment results demonstrated that the hardware system run steadily under the condition of high resolution and frequency, in addition, the edge effect improved greatly after image processing.


2014 ◽  
Vol 543-547 ◽  
pp. 1525-1528 ◽  
Author(s):  
Qing He Liu ◽  
Yan Chao Rong

A novel electro-hydraulic brake system configuration was designed by adding a hydraulic control module on conventional brake system with ABS, which achieves independent hydraulic braking force control for each wheel. With the purpose of improving energy recovery efficiency, a braking force distribution algorithm based on ECE regulations and motor external characteristics was proposed. Then further simulation verification was made to demonstrate its availability by using ADVISOR. Finally, a key aspect specific to independent hydraulic braking force control, a bilinear interpolation algorithm was defined and a hardware test was carried out. The results verify the feasibility and effectiveness of this algorithm.


2013 ◽  
Vol 634-638 ◽  
pp. 3989-3993
Author(s):  
Hui Wang ◽  
Guo Jia Li ◽  
Jun Hui Pan

Before the large capacity and engineering image is analyzed carefully, which need to be effective scaled. The subsequent analysis and calculation to engineering image is subjected by image quality and scaling time. According to scaling research of large capacity engineering image, the effect for image scaling by various interpolation algorithm is individual analyzed, and more appropriate algorithm is selected. The experimental results show that the engineering image of best effect is got, when it is high-expansion scaled by double cubic interpolation, and the bilinear interpolation is more suitable for low multiple scaling image.


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