scholarly journals Embedded Software Engineering Approach to Implement BCM5354 Processor Performance

2016 ◽  
Vol 1 (1) ◽  
pp. 41
Author(s):  
Varuna Eswer ◽  
Sanket Suresh Naik Dessai
Keyword(s):  
Operating System ◽  
Software Engineering ◽  
Embedded System ◽  
Memory Management ◽  
Performance Metrics ◽  
Critical Factor ◽  
Design System ◽  
Engineering Approach ◽  
Processor Performance ◽  
Initial Stage

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS) using software engineering approach. Software engineering providing better clearity for the system developemt and its performance analysis.In the initial stage if the requirement analysis for the performance measurment sort very clearly,the methodologies for the implementation becomes very economical without any ambigunity.In this paper a implementation is proposed to determine the processor performance metrics using a software engineering approach considering the counting of the respective cache and TLB management instruction execution, which is an event that is measurable with the use of dedicated counters. The lack of hardware counters in the MIPS32 processor results in the usage of software based event counters that are defined in the kernel. This paper implements a subset of MIPS32 processor performance measurement metrics using software based counters. Techniques were developed to overcome the challenges posed by the kernel source code. To facilitate better understanding of the implementation procedure of the software based processor performance counters; use-case analysis diagram, flow charts, screen shots, and knowledge nuggets are supplemented along with histograms of the cache and TLB events data generated by the proposed implementation. Twenty-seven metrics have been identified and implemented to provide data related to the events of the L1 cache and TLB on the MIPS32 processor. The generated data can be used in tuning of compiler, OS memory management design, system benchmarking, scalability, analysing architectural issues, address space analysis, understanding bus communication, kernel profiling, and workload characterisation.

scholarly journals Embedded Software Testing to Determine BCM5354 Processor Performance

2016 ◽  
Vol 1 (3) ◽  
pp. 121
Author(s):  
Sanket Suresh Naik Dessai ◽  
Varuna Eswer
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Memory Management ◽  
Critical Factor ◽  
Testing Procedure ◽  
Design System ◽  
Translation Lookaside Buffer ◽  
Processor Performance ◽  
Events Data ◽  
Embedded Testing

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation of embedded testing procedure to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS). The implementation proposed for embedded testing in the paper considers the counting of the respective cache and TLB management instruction execution, which is an event that is measurable with the use of dedicated counters. The lack of hardware counters in the MIPS32 processor results in the usage of software based event counters that are defined in the kernel. This paper implements embedding testbed with a subset of MIPS32 processor performance measurement metrics using software based counters. Techniques were developed to overcome the challenges posed by the kernel source code. To facilitate better understanding of the testbed implementation procedure of the software based processor performance counters; use-case analysis diagram, flow charts, screen shots, and knowledge nuggets are supplemented along with histograms of the cache and TLB events data generated by the proposed implementation. In this testbed twenty-seven metrics have been identified and implemented to provide data related to the events of the L1 cache and TLB on the MIPS32 processor. The generated data can be used in tuning of compiler, OS memory management design, system benchmarking, scalability, analysing architectural issues, address space analysis, understanding bus communication, kernel profiling, and workload characterisation.

scholarly journals Processor performance metrics analysis and implementation for MIPS using an open source OS

2021 ◽  
Vol 10 (2) ◽  
pp. 137
Author(s):  
Varuna Eswer ◽  
Sanket S Naik Dessai
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Memory Management ◽  
Performance Metrics ◽  
Future Research ◽  
Address Space ◽  
Translation Lookaside Buffer ◽  
Processor Performance ◽  
Processor Efficiency ◽  
Hardware Counters

<p><span>Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varing load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction exxecution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twenty-seven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analysing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterisation and kernel profiling.</span></p>

scholarly journals MRDRL-ROS: a Multi Robot Deep Reinforcement Learning Platform based on Robot Operating System

2021 ◽  
Vol 2113 (1) ◽  
pp. 012086
Author(s):  
Zhongxuan Cai ◽  
Zhen Liang ◽  
Jing Ren
Keyword(s):  
Operating System ◽  
Reinforcement Learning ◽  
Software Engineering ◽  
Learning Environment ◽  
Building Blocks ◽  
Experimental Results ◽  
Robot Operating System ◽  
Engineering Approach ◽  
Learning Platform ◽  
Diverse Environment

Abstract Deep reinforcement learning (DRL) has greatly improved the intelligence of AI in recent years and the community has proposed several common software to facilitate the development of DRL. However, in robotics the utility of common DRL software is limited and the development is time-consuming due to the complexity of various robot software. In this paper, we propose a software engineering approach leveraging modularity to facilitate robot DRL development. The platform decouples learning environment into task, simulator and hierarchical robot modules, which in turn enables diverse environment generation using existing modules as building blocks, regardless of the underlying robot software details. Experimental results show that our platform provides composable environment building, introduces high module reuse and efficiently facilitates robot DRL.

Algorithmic Cost Modeling: Statistical Software Engineering Approach

2006 ◽  
Vol 1 (1) ◽  
pp. 19-24 ◽  
Author(s):  
Kumar Saurabh ◽  
◽  
Haragopala P.V. Pamula ◽  
Keyword(s):  
Software Engineering ◽  
Cost Modeling ◽  
Statistical Software ◽  
Engineering Approach

scholarly journals Research on Innovative Business Plan. Smart Cattle Farming Using Artificial Intelligent Robotic Process Automation

Agriculture ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 430
Author(s):  
Diana Elena Micle ◽  
Florina Deiac ◽  
Alexandru Olar ◽  
Raul Florentin Drența ◽  
Cristian Florean ◽  
...  
Keyword(s):  
Performance Metrics ◽  
Critical Factor ◽  
Remote Work ◽  
Process Automation ◽  
Continuous Training ◽  
Robotic Process Automation ◽  
Focus Group Meeting ◽  
Information And Communication ◽  
Cattle Farming ◽  
Agricultural Business

Integrating livestock management with the required devices and sensors is now seen as a critical factor in the agricultural sector’s long-term success. The findings revealed that the agricultural business sector is open to implementing Information and Communication Technology (ICT) solutions, so the aim of this paper is to determine how advantageous it is for Romanian farmers to invest in a project that employs smart cattle farming methods that incorporate Artificial Intelligence (AI), Robotic Process Automation (RPA) and the Internet of Things (IOT). An unstructured interview was used to gather empirical evidence during a focus group meeting. Analyzing the selected primary performance metrics, it was projected that the farm’s profitability would increase by 19 percent, productivity would increase by 21 percent, and the farm’s environmental impact would decrease by 22 percent. Automation and remote work would help minimize the farm’s worker burden while also making control panels, decision-making files, and data analysis more available. In order for the domain to be as prosperous as possible, farmers must be made aware of the benefits of using these emerging technologies for closing the gap between farmers and Information Technology (IT) solution providers, and this can be accomplished through continuous training for both farmers and their technology vendors.

scholarly journals Memory Management in Operating System

2018 ◽  
Vol Volume-2 (Issue-5) ◽  
pp. 2346-2347
Author(s):  
Durgesh Raghuvanshi ◽  
Keyword(s):  
Operating System ◽  
Memory Management
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