scholarly journals Embedded Software Testing to Determine BCM5354 Processor Performance

2016 ◽  
Vol 1 (3) ◽  
pp. 121
Author(s):  
Sanket Suresh Naik Dessai ◽  
Varuna Eswer
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Memory Management ◽  
Critical Factor ◽  
Testing Procedure ◽  
Design System ◽  
Translation Lookaside Buffer ◽  
Processor Performance ◽  
Events Data ◽  
Embedded Testing

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation of embedded testing procedure to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS). The implementation proposed for embedded testing in the paper considers the counting of the respective cache and TLB management instruction execution, which is an event that is measurable with the use of dedicated counters. The lack of hardware counters in the MIPS32 processor results in the usage of software based event counters that are defined in the kernel. This paper implements embedding testbed with a subset of MIPS32 processor performance measurement metrics using software based counters. Techniques were developed to overcome the challenges posed by the kernel source code. To facilitate better understanding of the testbed implementation procedure of the software based processor performance counters; use-case analysis diagram, flow charts, screen shots, and knowledge nuggets are supplemented along with histograms of the cache and TLB events data generated by the proposed implementation. In this testbed twenty-seven metrics have been identified and implemented to provide data related to the events of the L1 cache and TLB on the MIPS32 processor. The generated data can be used in tuning of compiler, OS memory management design, system benchmarking, scalability, analysing architectural issues, address space analysis, understanding bus communication, kernel profiling, and workload characterisation.

scholarly journals Embedded Software Engineering Approach to Implement BCM5354 Processor Performance

2016 ◽  
Vol 1 (1) ◽  
pp. 41
Author(s):  
Varuna Eswer ◽  
Sanket Suresh Naik Dessai
Keyword(s):  
Operating System ◽  
Software Engineering ◽  
Embedded System ◽  
Memory Management ◽  
Performance Metrics ◽  
Critical Factor ◽  
Design System ◽  
Engineering Approach ◽  
Processor Performance ◽  
Initial Stage

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS) using software engineering approach. Software engineering providing better clearity for the system developemt and its performance analysis.In the initial stage if the requirement analysis for the performance measurment sort very clearly,the methodologies for the implementation becomes very economical without any ambigunity.In this paper a implementation is proposed to determine the processor performance metrics using a software engineering approach considering the counting of the respective cache and TLB management instruction execution, which is an event that is measurable with the use of dedicated counters. The lack of hardware counters in the MIPS32 processor results in the usage of software based event counters that are defined in the kernel. This paper implements a subset of MIPS32 processor performance measurement metrics using software based counters. Techniques were developed to overcome the challenges posed by the kernel source code. To facilitate better understanding of the implementation procedure of the software based processor performance counters; use-case analysis diagram, flow charts, screen shots, and knowledge nuggets are supplemented along with histograms of the cache and TLB events data generated by the proposed implementation. Twenty-seven metrics have been identified and implemented to provide data related to the events of the L1 cache and TLB on the MIPS32 processor. The generated data can be used in tuning of compiler, OS memory management design, system benchmarking, scalability, analysing architectural issues, address space analysis, understanding bus communication, kernel profiling, and workload characterisation.

scholarly journals Processor performance metrics analysis and implementation for MIPS using an open source OS

2021 ◽  
Vol 10 (2) ◽  
pp. 137
Author(s):  
Varuna Eswer ◽  
Sanket S Naik Dessai
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Memory Management ◽  
Performance Metrics ◽  
Future Research ◽  
Address Space ◽  
Translation Lookaside Buffer ◽  
Processor Performance ◽  
Processor Efficiency ◽  
Hardware Counters

<p><span>Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varing load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction exxecution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twenty-seven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analysing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterisation and kernel profiling.</span></p>

scholarly journals Memory Management in Operating System

2018 ◽  
Vol Volume-2 (Issue-5) ◽  
pp. 2346-2347
Author(s):  
Durgesh Raghuvanshi ◽  
Keyword(s):  
Operating System ◽  
Memory Management

Linux Based Mobile Operating Systems

2011 ◽  
pp. 35-50
Author(s):  
Lee Chao
Keyword(s):  
Operating System ◽  
User Interface ◽  
Mobile Learning ◽  
Operating Systems ◽  
Memory Management ◽  
Process Management ◽  
Management Process ◽  
Interface Management ◽  
Device Management ◽  
History Of

In today’s mobile computing, Linux plays a significant role. The Linux kernel has been adopted by a variety of mobile operating systems to handle tasks such as device management, memory management, process management, networking, power management, application interface management, and user interface management. This chapter introduces Linux based mobile operating systems installed on various mobile devices. It first gives a brief introduction of the history of mobile Linux. Then, the chapter introduces the mobile Linux features that can be used to meet the mobile learning requirements. The last part of the chapter presents strategies on selecting a Linux based operating system for a particular mobile learning project.

scholarly journals A Case for Security-Aware Design-Space Exploration of Embedded Systems

2020 ◽  
Vol 10 (3) ◽  
pp. 22
Author(s):  
Andy D. Pimentel
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Design Space Exploration ◽  
Design Space ◽  
Space Exploration ◽  
Systems Design ◽  
Design System ◽  
Multi Objective Optimization ◽  
Multi Objective ◽  
Trade Offs

As modern embedded systems are becoming more and more ubiquitous and interconnected, they attract a world-wide attention of attackers and the security aspect is more important than ever during the design of those systems. Moreover, given the ever-increasing complexity of the applications that run on these systems, it becomes increasingly difficult to meet all security criteria. While extra-functional design objectives such as performance and power/energy consumption are typically taken into account already during the very early stages of embedded systems design, system security is still mostly considered as an afterthought. That is, security is usually not regarded in the process of (early) design-space exploration of embedded systems, which is the critical process of multi-objective optimization that aims at optimizing the extra-functional behavior of a design. This position paper argues for the development of techniques for quantifying the ’degree of secureness’ of embedded system design instances such that these can be incorporated in a multi-objective optimization process. Such technology would allow for the optimization of security aspects of embedded systems during the earliest design phases as well as for studying the trade-offs between security and the other design objectives such as performance, power consumption and cost.

Design of Mini Multi-Process Micro-Kernel Embedded OS on ARM

2013 ◽  
Vol 347-350 ◽  
pp. 1780-1785
Author(s):  
Bo Qu ◽  
Zhao Zhi Wu
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Process Management ◽  
Priority Queue ◽  
Communication Process ◽  
Application Development ◽  
Memory Space ◽  
Embedded Os ◽  
Technical Details ◽  
Inter Process Communication

This paper describes the design and implementation of a mini multi-process micro-kernel embedded Unix-like operating system on ARM platform in technical details, including MMU and memory space mapping, init process, inter-process communication, process management, TTY and tiny shell, multi-level priority-queue schedule, and signaling. The mini OS is developed on Linux platform with GNU tool chain by the author of this paper. The architecture of the mini OS is analogous to that of Minix. Based on it, other operating system components such as file system, network management, and copy-on-write can be appended to form a full-featured embedded operating system. The mini OS can be used for both embedded system application development and related curriculum teaching.

Sign in / Sign up

Export Citation Format

Share Document