scholarly journals Processor performance metrics analysis and implementation for MIPS using an open source OS

2021 ◽  
Vol 10 (2) ◽  
pp. 137
Author(s):  
Varuna Eswer ◽  
Sanket S Naik Dessai
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Memory Management ◽  
Performance Metrics ◽  
Future Research ◽  
Address Space ◽  
Translation Lookaside Buffer ◽  
Processor Performance ◽  
Processor Efficiency ◽  
Hardware Counters

<p><span>Processor efficiency is a important in embedded system. The efficiency of the processor depends on the L1 cache and translation lookaside buffer (TLB). It is required to understand the L1 cache and TLB performances during varied load for the execution on the processor and hence studies the performance of the varing load and its performance with caches with MIPS and operating system (OS) are studied in this paper. The proposed methods of implementation in the paper considers the counting of the instruction exxecution for respective cache and TLB management and the events are measured using a dedicated counters in software. The software counters are used as there are limitation to hardware counters in the MIPS32. Twenty-seven metrics are considered for analysis and proper identification and implemented for the performance measurement of L1 cache and TLB on the MIPS32 processor. The generated data helps in future research in compiler tuning, memory management design for OS, analysing architectural issues, system benchmarking, scalability, address space analysis, studies of bus communication among processor and its workload sharing characterisation and kernel profiling.</span></p>

scholarly journals Embedded Software Testing to Determine BCM5354 Processor Performance

2016 ◽  
Vol 1 (3) ◽  
pp. 121
Author(s):  
Sanket Suresh Naik Dessai ◽  
Varuna Eswer
Keyword(s):  
Operating System ◽  
Embedded System ◽  
Memory Management ◽  
Critical Factor ◽  
Testing Procedure ◽  
Design System ◽  
Translation Lookaside Buffer ◽  
Processor Performance ◽  
Events Data ◽  
Embedded Testing

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation of embedded testing procedure to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS). The implementation proposed for embedded testing in the paper considers the counting of the respective cache and TLB management instruction execution, which is an event that is measurable with the use of dedicated counters. The lack of hardware counters in the MIPS32 processor results in the usage of software based event counters that are defined in the kernel. This paper implements embedding testbed with a subset of MIPS32 processor performance measurement metrics using software based counters. Techniques were developed to overcome the challenges posed by the kernel source code. To facilitate better understanding of the testbed implementation procedure of the software based processor performance counters; use-case analysis diagram, flow charts, screen shots, and knowledge nuggets are supplemented along with histograms of the cache and TLB events data generated by the proposed implementation. In this testbed twenty-seven metrics have been identified and implemented to provide data related to the events of the L1 cache and TLB on the MIPS32 processor. The generated data can be used in tuning of compiler, OS memory management design, system benchmarking, scalability, analysing architectural issues, address space analysis, understanding bus communication, kernel profiling, and workload characterisation.

scholarly journals Embedded Software Engineering Approach to Implement BCM5354 Processor Performance

2016 ◽  
Vol 1 (1) ◽  
pp. 41
Author(s):  
Varuna Eswer ◽  
Sanket Suresh Naik Dessai
Keyword(s):  
Operating System ◽  
Software Engineering ◽  
Embedded System ◽  
Memory Management ◽  
Performance Metrics ◽  
Critical Factor ◽  
Design System ◽  
Engineering Approach ◽  
Processor Performance ◽  
Initial Stage

Efficiency of a processor is a critical factor for an embedded system. One of the deciding factors for efficiency is the functioning of the L1 cache and Translation Lookaside Buffer (TLB). Certain processors have the L1 cache and TLB managed by the operating system, MIPS32 is one such processor. The performance of the L1 cache and TLB necessitates a detailed study to understand its management during varied load on the processor. This paper presents an implementation to analyse the performance of the MIPS32 processor L1 cache and TLB management by the operating system (OS) using software engineering approach. Software engineering providing better clearity for the system developemt and its performance analysis.In the initial stage if the requirement analysis for the performance measurment sort very clearly,the methodologies for the implementation becomes very economical without any ambigunity.In this paper a implementation is proposed to determine the processor performance metrics using a software engineering approach considering the counting of the respective cache and TLB management instruction execution, which is an event that is measurable with the use of dedicated counters. The lack of hardware counters in the MIPS32 processor results in the usage of software based event counters that are defined in the kernel. This paper implements a subset of MIPS32 processor performance measurement metrics using software based counters. Techniques were developed to overcome the challenges posed by the kernel source code. To facilitate better understanding of the implementation procedure of the software based processor performance counters; use-case analysis diagram, flow charts, screen shots, and knowledge nuggets are supplemented along with histograms of the cache and TLB events data generated by the proposed implementation. Twenty-seven metrics have been identified and implemented to provide data related to the events of the L1 cache and TLB on the MIPS32 processor. The generated data can be used in tuning of compiler, OS memory management design, system benchmarking, scalability, analysing architectural issues, address space analysis, understanding bus communication, kernel profiling, and workload characterisation.

scholarly journals Address Space Layout Randomization Comparative Analysis on Windows 10 and Ubuntu 18.04 LTS

2021 ◽  
Vol 7 (1) ◽  
pp. 26
Author(s):  
Raquel Vázquez Díaz ◽  
Martiño Rivera-Dourado ◽  
Rubén Pérez-Jove ◽  
Pilar Vila Avendaño ◽  
José M. Vázquez-Naya
Keyword(s):  
Operating System ◽  
Comparative Analysis ◽  
Operating Systems ◽  
Memory Management ◽  
Address Space ◽  
Memory Protection ◽  
Partial Correlations ◽  
Feature Memory ◽  
Space Layout ◽  
Address Space Layout Randomization

Memory management is one of the main tasks of an Operating System, where the data of each process running in the system is kept. In this context, there exist several types of attacks that exploit memory-related vulnerabilities, forcing Operating Systems to feature memory protection techniques that make difficult to exploit them. One of these techniques is ASLR, whose function is to introduce randomness into the virtual address space of a process. The goal of this work was to measure, analyze and compare the behavior of ASLR on the 64-bit versions of Windows 10 and Ubuntu 18.04 LTS. The results have shown that the implementation of ASLR has improved significantly on these two Operating Systems compared to previous versions. However, there are aspects, such as partial correlations or a frequency distribution that is not always uniform, so it can still be improved.

scholarly journals Shall I Work with Them? A Knowledge Graph-Based Approach for Predicting Future Research Collaborations

Entropy ◽  
2021 ◽  
Vol 23 (6) ◽  
pp. 664
Author(s):  
Nikos Kanakaris ◽  
Nikolaos Giarelis ◽  
Ilias Siachos ◽  
Nikos Karacapilidis
Keyword(s):  
Language Processing ◽  
Scientific Knowledge ◽  
Link Prediction ◽  
Performance Metrics ◽  
Future Research ◽  
Knowledge Graph ◽  
Prediction Problem ◽  
Textual Information ◽  
Research Collaborations ◽  
Processing Techniques

We consider the prediction of future research collaborations as a link prediction problem applied on a scientific knowledge graph. To the best of our knowledge, this is the first work on the prediction of future research collaborations that combines structural and textual information of a scientific knowledge graph through a purposeful integration of graph algorithms and natural language processing techniques. Our work: (i) investigates whether the integration of unstructured textual data into a single knowledge graph affects the performance of a link prediction model, (ii) studies the effect of previously proposed graph kernels based approaches on the performance of an ML model, as far as the link prediction problem is concerned, and (iii) proposes a three-phase pipeline that enables the exploitation of structural and textual information, as well as of pre-trained word embeddings. We benchmark the proposed approach against classical link prediction algorithms using accuracy, recall, and precision as our performance metrics. Finally, we empirically test our approach through various feature combinations with respect to the link prediction problem. Our experimentations with the new COVID-19 Open Research Dataset demonstrate a significant improvement of the abovementioned performance metrics in the prediction of future research collaborations.

scholarly journals Opportunistic Large Array Propagation Models: A Comprehensive Survey

Sensors ◽  
2021 ◽  
Vol 21 (12) ◽  
pp. 4206
Author(s):  
Farhan Nawaz ◽  
Hemant Kumar ◽  
Syed Ali Hassan ◽  
Haejoon Jung
Keyword(s):  
Energy Efficient ◽  
Large Scale ◽  
Performance Metrics ◽  
Experimental Studies ◽  
Cooperative Transmission ◽  
Analytical Models ◽  
Future Research ◽  
Large Array ◽  
Propagation Models ◽  
Comprehensive Survey

Enabled by the fifth-generation (5G) and beyond 5G communications, large-scale deployments of Internet-of-Things (IoT) networks are expected in various application fields to handle massive machine-type communication (mMTC) services. Device-to-device (D2D) communications can be an effective solution in massive IoT networks to overcome the inherent hardware limitations of small devices. In such D2D scenarios, given that a receiver can benefit from the signal-to-noise-ratio (SNR) advantage through diversity and array gains, cooperative transmission (CT) can be employed, so that multiple IoT nodes can create a virtual antenna array. In particular, Opportunistic Large Array (OLA), which is one type of CT technique, is known to provide fast, energy-efficient, and reliable broadcasting and unicasting without prior coordination, which can be exploited in future mMTC applications. However, OLA-based protocol design and operation are subject to network models to characterize the propagation behavior and evaluate the performance. Further, it has been shown through some experimental studies that the most widely-used model in prior studies on OLA is not accurate for networks with networks with low node density. Therefore, stochastic models using quasi-stationary Markov chain are introduced, which are more complex but more exact to estimate the key performance metrics of the OLA transmissions in practice. Considering the fact that such propagation models should be selected carefully depending on system parameters such as network topology and channel environments, we provide a comprehensive survey on the analytical models and framework of the OLA propagation in the literature, which is not available in the existing survey papers on OLA protocols. In addition, we introduce energy-efficient OLA techniques, which are of paramount importance in energy-limited IoT networks. Furthermore, we discuss future research directions to combine OLA with emerging technologies.

scholarly journals Development and Formative Evaluation of a Low-Fidelity Equine Castration Model for Veterinary Education

2021 ◽  
Vol 8 ◽  
Author(s):  
M. Katie Sheats ◽  
Megan J. Burke ◽  
James B. Robertson ◽  
Katherine E. Fiebrandt ◽  
Callie A. Fogle
Keyword(s):  
Student Performance ◽  
Student Attitudes ◽  
Formative Evaluation ◽  
Performance Metrics ◽  
Early Stage ◽  
Future Research ◽  
Student Survey ◽  
Significant Difference ◽  
Veterinary Faculty ◽  
Fidelity Model

Entrustable Professional Activities (EPAs) are units of activity that early-stage professionals perform in the workplace that necessitate simultaneous integration of multiple competencies. EPA #6 requires students to perform a common surgical procedure on a stable patient, including pre-operative and post-operative management. Castration is one of the most common surgeries performed by equine primary care practitioners and is considered an “entry-level competency” for veterinary graduates entering equine private practice, however, to our knowledge there are no equine castration models available for veterinary student education. Therefore, we developed an inexpensive, low-fidelity model of equine field castration and evaluated it using a mixed-methods approach. Two different groups of students, with or without model experience, completed surveys before and after live horse castration. Students who used the model also completed model specific surveys. Videos of the students completing the model were evaluated by at least two different equine veterinary faculty using a 15-point rubric, and inter-rater reliability of the rubric was determined. After completing the model, students reflected on strengths and weaknesses of their performance. From our student survey results, we determined that student attitudes toward the model were mostly positive. Interestingly, there were several student attitudes toward the model that became significantly more favorable after live horse castration. Prior to live horse castration, there was no significant difference in confidence in model vs. no-model groups. Following live horse castration, students who used the model had higher confidence in procedure preparation and hand-ties than students who did not use the model, but they had lower scores for confidence during patient recovery. When reflecting on model castration, students most commonly cited preparation and surgical description as strengths, and ligature placement and hand-ties as weaknesses. Experts provided several suggestions to improve the model, including incorporation of emasculators and the need for better model stabilization. Our findings suggest that both students and veterinary educators feel that this low-fidelity model has educational value. Rubric performance metrics were favorable, but additional steps are needed to improve grading consistency among educators. Future research will determine whether student performance on the model is predictive of competence score during live-horse castration.

scholarly journals Memory Management in Operating System

2018 ◽  
Vol Volume-2 (Issue-5) ◽  
pp. 2346-2347
Author(s):  
Durgesh Raghuvanshi ◽  
Keyword(s):  
Operating System ◽  
Memory Management

The mungi single-address-space operating system

1998 ◽  
Vol 28 (9) ◽  
pp. 901-928 ◽  
Author(s):  
Gernot Heiser ◽  
Kevin Elphinstone ◽  
Jerry Vochteloo ◽  
Stephen Russell ◽  
Jochen Liedtke
Keyword(s):  
Operating System ◽  
Address Space

Digital supply chain performance metrics: a literature review

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Faisal Rasool ◽  
Marco Greco ◽  
Michele Grimaldi
Keyword(s):  
Supply Chain ◽  
Literature Review ◽  
Systematic Literature Review ◽  
Performance Metrics ◽  
Research Process ◽  
Future Research ◽  
Balance Scorecard ◽  
Content Type ◽  
Previous Decade ◽  
Qualitative Performance

Purpose In the previous decade, a substantial amount of research has been undertaken to measure the digitalized supply chain (DSC) performance. This paper aims to present a systematic literature review on DSC performance measurement metrics to apprehend current practices, recognize gaps and advocate future research itineraries. Design/methodology/approach To guarantee a replicable, rigorous and transparent research process, the authors used a systematic literature review methodology to synthesize the research. A combination of 25 keywords was used to obtain 248 scientific studies in the first step. The balance scorecard (BSC) model was used to categorize 299 gathered performance metrics into 4 BSC perspectives. Findings The review highlighted the need for qualitative performance measuring metrics for DSC. During the review, only one study was identified that primarily focused on developing performance metrics for DSC. Additionally, the review identified that metrics related to internal and financial perspectives received the most attention while the “growth and learning” perspective received the least attention. The review also identified that external partners, such as distributors and suppliers, were virtually ignored in previous literature. Originality/value Although numerous literature reviews have been conducted in the past on the performance measuring metrics for supply chain management, no literature review aiming to synthesize the measuring metrics for DSC has yet been undertaken.

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