scholarly journals A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

2017 ◽  
Vol 6 (1) ◽  
pp. 24 ◽  
Author(s):  
Mohammad Rafi Lone ◽  
Najeed- Ud-Din
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Speed ◽  
Parallel Implementation ◽  
Critical Path ◽  
Low Complexity ◽  
Discrete Wavelet ◽  
Throughput Optimization ◽  
Xilinx Fpga ◽  
Parallel Fashion

For real-time applications, efficient VLSI implementation of DWT is desired. In this paper, DWT architecture based on retiming for pipelining and unfolding is presented. The architecture is based on lifting one-dimensional Cohen-Daubechies-Feauveau (CDF) (5,3) wavelet filter, which is easily extended to 2-D implementation. It consists of low complexity and easily repeatable components. This paper is focused on the critical path minimization and throughput optimization at the same time. The architecture has been implemented on Virtex 6 Xilinx FPGA platform. The implementation results show that the critical path is minimized four to five times, while throughput is doubled, making the overall architecture approximately ten times faster when compared with the conventional lifting-based DWT architecture. Further with parallel implementation, the throughput has doubled without any increase in number of row buffers, implying that the architecture is memory efficient as well. The even and odd rows of the image are scanned in parallel fashion. To perform the 2-D DWT transform of an image of size 15 Megapixels, it takes 16.86 ms, which implies 59 images of that size can be processed in one second. This can be utilized for real-time video processing applications even for high resolution videos.

FPGA Implementation of a High-Speed Two Dimensional Discrete Wavelet Transform

2013 ◽  
Vol 479-480 ◽  
pp. 508-512
Author(s):  
Chin Fa Hsieh ◽  
Tsung Han Tsai
Keyword(s):  
Wavelet Transform ◽  
Discrete Wavelet Transform ◽  
Real Time ◽  
High Speed ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Image Sensor ◽  
Discrete Wavelet ◽  
Two Dimensional ◽  
Clock Period

This paper proposes high-speed VLSI architecture for implementing a forward two-dimensional discrete wavelet transform (2D DWT). The architecture is based on 2D DWT mathematical formulae. A pipelined scheme is used to increase the clock rate, which allows its critical path to take only one adder delay. The proposed design enables 100% hardware use and faster computing than other 2D DWT architecture. It is easily extended to multilevel decomposition because of its regular structure. It requires N/2 by N/2 clock cycles for k-level analysis of an N by N image. The proposed architecture was coded in VerilogHDL and verified on a real time platform which uses a CMOS image sensor, a field-programmable gate array (FPGA) and a TFT-LCD panel. In the simulation, the design worked with a clock period of 132.38MHz. It can be used as an independent IP core for various real-time applications.

The Design of Real-Time and High-Speed Video Processing Platform for Aerial UAV Based on DM642

2014 ◽  
Vol 1061-1062 ◽  
pp. 1186-1189
Author(s):  
Ming Zhe Wei ◽  
Wan Wei Tang
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Speed ◽  
Rapid Development ◽  
Processing System ◽  
Video Signal ◽  
Good Effect ◽  
Time Data ◽  
Spatial Interference ◽  
On Chip

With the rapid development of aerial UAV (Unmanned Aerial Vehicle), the design of real-time data acquisition and transmission system for the video signal has a new applied field. It is different from traditional video acquisition and processing system, aerial video signal has the problems of screen jitter and spatial interference. The processing algorithm of aerial UAV airborne video signal is put forward in the paper, and the platform of high speed procession is constructed based on chip TMS320DM642, and get a good effect.

scholarly journals Low-Complexity Hardware Interleaver/Deinterleaver for IEEE 802.11a/g/n WLAN

VLSI Design ◽  
2012 ◽  
Vol 2012 ◽  
pp. 1-7
Author(s):  
Zhen-dong Zhang ◽  
Bin Wu ◽  
Yu-mei Zhou ◽  
Xin Zhang
Keyword(s):  
High Speed ◽  
Critical Path ◽  
Low Complexity ◽  
Cmos Technology ◽  
Path Delay ◽  
Hardware Complexity ◽  
Ieee 802.11A ◽  
Comparison Results ◽  
Mathematical Formulas ◽  
High Flexibility

A high-speed low-complexity hardware interleaver/deinterleaver is presented. It supports all 77 802.11n high-throughput (HT) modulation and coding schemes (MCSs) with short and long guard intervals and the 8 non-HT MCSs defined in 802.11a/g. The paper proposes a design methodology that distributes the three permutations of an interleaver to both write address and read address. The methodology not only reduces the critical path delay but also facilitates the address generation. In addition, the complex mathematical formulas are replaced with optimized hardware structures in which hardware intensive dividers and multipliers are avoided. Using 0.13 um CMOS technology, the cell area of the proposed interleaver/deinterleaver is 0.07 mm2, and the synthesized maximal working frequency is 400 MHz. Comparison results show that it outperforms the three other similar works with respect to hardware complexity and max frequency while maintaining high flexibility.

scholarly journals Low Complexity FFT Factorization for CS Reconstruction

2020 ◽  
Vol 9 (3) ◽  
pp. 438-442
Keyword(s):  
Real Time ◽  
High Speed ◽  
Performance Metrics ◽  
Matching Pursuit ◽  
Matrix Multiplication ◽  
Low Complexity ◽  
Orthogonal Matching Pursuit ◽  
Reconstruction Algorithms ◽  
Wide Range ◽  
Computationally Intensive

In this paper is presented a novel area efficient Fast Fourier transform (FFT) for real-time compressive sensing (CS) reconstruction. Among various methodologies used for CS reconstruction algorithms, Greedy-based orthogonal matching pursuit (OMP) approach provides better solution in terms of accurate implementation with complex computations overhead. Several computationally intensive arithmetic operations like complex matrix multiplication are required to formulate correlative vectors making this algorithm highly complex and power consuming hardware implementation. Computational complexity becomes very important especially in complex FFT models to meet different operational standards and system requirements. In general, for real time applications, FFT transforms are required for high speed computations as well as with least possible complexity overhead in order to support wide range of applications. This paper presents an hardware efficient FFT computation technique with twiddle factor normalization for correlation optimization in orthogonal matching pursuit (OMP). Experimental results are provided to validate the performance metrics of the proposed normalization techniques against complexity and energy related issues. The proposed method is verified by FPGA synthesizer, and validated with appropriate currently available comparative analyzes.

An Intelligent High-Frame-Rate Video Logging System for Abnormal Behavior Analysis

2011 ◽  
Vol 23 (1) ◽  
pp. 53-65 ◽  
Author(s):  
Yao-DongWang ◽  
◽  
Idaku Ishii ◽  
Takeshi Takaki ◽  
Kenji Tajima ◽  
...  
Keyword(s):  
Real Time ◽  
Video Processing ◽  
High Speed ◽  
Vision System ◽  
Video Recording ◽  
Frame Rate ◽  
Abnormal Behavior ◽  
High Frame Rate ◽  
Abnormal Behavior Detection ◽  
Abnormal Behaviors

This paper introduces a high-speed vision system called IDP Express, which can execute real-time image processing and High-Frame-Rate (HFR) video recording simultaneously. In IDP Express, 512×512 pixel images from two camera heads and the processed results on a dedicated FPGA (Field Programmable Gate Array) board are transferred to standard PC memory at a rate of 1000 fps or more. Owing to the simultaneous HFR video processing and recording, IDP Express can be used as an intelligent video logging system for long-term high-speed phenomenon analysis. In this paper, a real-time abnormal behavior detection algorithm was implemented on IDP-Express to capture HFR videos of crucial moments of unpredictable abnormal behaviors in high-speed periodic motions. Several experiments were performed for a high-speed slider machine with repetitive operation at a frequency of 15 Hz and videos of the abnormal behaviors were automatically recorded to verify the effectiveness of our intelligent HFR video logging system.

A Memory Efficient, Multiplierless & Modular VLSI Architecture of 1D/2D Re-Configurable 9/7 & 5/3 DWT Filters Using Distributed Arithmetic

2020 ◽  
Vol 29 (09) ◽  
pp. 2050151
Author(s):  
Anirban Chakraborty ◽  
Ayan Banerjee
Keyword(s):  
Real Time ◽  
Critical Path ◽  
Vlsi Architecture ◽  
Computation Time ◽  
Discrete Wavelet ◽  
Path Delay ◽  
Distributed Arithmetic ◽  
Real Time Imaging ◽  
Input Mode ◽  
Memory Efficient

Dedicated hardware for “Discrete Wavelet Transform” (DWT) is at high demand for real-time imaging operations in any standalone electronic devices, as DWT is being extensively utilized for most of the transform-domain imagery applications. Various DWT algorithms exist in the literature facilitating its software implementations which are generally unsuitable for real-time imaging in any stand-alone devices due to their power intensiveness and huge computation time. In this paper, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. Our proposed architecture, which mingles the advantages of convolutional and lifting DWT while discarding their notable disadvantages, is made area and memory efficient by exploiting “Distributed Arithmetic’ (DA) in our own ingenious way. Almost 90% reduction in the memory size than other notable architectures is reported. In our proposed architecture, both the 9/7 and 5/3 DWT filters can be realized with a selection input, “mode”. With the introduction of DA, pipelining and parallelism are easily incorporated into our proposed 1D/2D DWT architectures. The area requirement and critical path delay are reduced to almost 38.3% and 50% than that of the latest remarkable designs. The performance of the proposed VLSI architecture also excels in real-time applications.

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