Performance Improvement in Nanoscale Ge–GaAs Heterojunction Junctionless Tunnel FET Using a Dual Material Gate

Journal of Low Power Electronics ◽

10.1166/jolpe.2014.1348 ◽

2014 ◽

Vol 10 (3) ◽

pp. 354-360 ◽

Author(s):

Bahniman Ghosh ◽

Shibir Basak ◽

Pranav Kumar Asthana

Keyword(s):

Performance Improvement ◽

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Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

Journal of Semiconductors ◽

10.1088/1674-4926/38/2/024001 ◽

2017 ◽

Vol 38 (2) ◽

pp. 024001 ◽

Author(s):

Sunny Anand ◽

R. K. Sarin

Keyword(s):

Gate Dielectric ◽

Rf Performance ◽

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Mathematical modeling insight of hetero gate dielectric-dual material gate-GAA-tunnel FET for VLSI/analog applications

Microsystem Technologies ◽

10.1007/s00542-016-2872-9 ◽

2016 ◽

Vol 23 (9) ◽

pp. 4091-4098 ◽

Author(s):

Jaya Madan ◽

R. S. Gupta ◽

Rishu Chaujar

Keyword(s):

Mathematical Modeling ◽

Gate Dielectric ◽

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High on-current and low threshold GaSb-InAs heterostructure dual-material DG tunnel-FET

2017 IEEE Region 10 Humanitarian Technology Conference (R10-HTC) ◽

10.1109/r10-htc.2017.8289006 ◽

2017 ◽

Author(s):

Md. Abdullah-Al-Kaiser ◽

Dip Joti Paul ◽

Quazi D. M. Khosru

Keyword(s):

Low Threshold ◽

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Electrostatic performance improvement of dual material cylindrical gate MOSFET using work-function modulation technique

Superlattices and Microstructures ◽

10.1016/j.spmi.2016.06.024 ◽

2016 ◽

Vol 97 ◽

pp. 212-220 ◽

Author(s):

Biswajit Jena ◽

Sidhartha Dash ◽

Guru Prasad Mishra

Keyword(s):

Work Function ◽

Performance Improvement ◽

Modulation Technique ◽

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Low-K Dielectric Pocket and Workfunction Engineering for DC and Analog/RF Performance Improvement in Dual Material Stack Gate Oxide Double Gate TFET

Silicon ◽

10.1007/s12633-020-00822-6 ◽

2020 ◽

Author(s):

Dharmender ◽

Kaushal Nigam

Keyword(s):

Performance Improvement ◽

Double Gate ◽

Rf Performance ◽

Dual Material ◽

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Analytical Modeling of Dual Material Gate All around Stack Architecture of Tunnel FET

2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID) ◽

10.1109/vlsid.2016.74 ◽

2016 ◽

Author(s):

N.B. Balamurugan ◽

G. Lakshmi Priya ◽

S. Manikandan ◽

G. Srimathi

Keyword(s):

Analytical Modeling ◽

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Performance improvement of Si Pocket-Tunnel FET with steep subthreshold slope and high ION/IOFF ratio

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology ◽

10.1109/icsict.2012.6467740 ◽

2012 ◽

Author(s):

Qianqian Huang ◽

Ru Huang ◽

Zhan Zhan ◽

Chunlei Wu ◽

Yingxin Qiu ◽

...

Keyword(s):

Performance Improvement ◽

Subthreshold Slope ◽

Steep Subthreshold Slope

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Insights into interlayer tunnel FET performance improvement: Lessons learned from graphene hexagonal boron nitride heterostructures

2016 74th Annual Device Research Conference (DRC) ◽

10.1109/drc.2016.7548442 ◽

2016 ◽

Author(s):

S. Kang ◽

N. Prasad ◽

H. C. P. Movva ◽

A. Rai ◽

K. Kim ◽

...

Keyword(s):

Boron Nitride ◽

Performance Improvement ◽

Hexagonal Boron Nitride ◽

Lessons Learned ◽

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An extensive electrostatic analysis of dual material gate all around tunnel FET (DMGAA-TFET)

Advances in Natural Sciences Nanoscience and Nanotechnology ◽

10.1088/2043-6262/7/2/025012 ◽

2016 ◽

Vol 7 (2) ◽

pp. 025012 ◽

Author(s):

S Dash ◽

G P Mishra

Keyword(s):

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Ambipolar Performance Improvement of Dual Material TFET Using Drain Underlap Engineering

2018 IEEE Electron Devices Kolkata Conference (EDKCON) ◽

10.1109/edkcon.2018.8770478 ◽

2018 ◽

Author(s):

P. Singh ◽

V. K. Chauhan ◽

D. D. Ray ◽

S. Dash ◽

G. P. Mishra

Keyword(s):

Performance Improvement ◽

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