Dual material gate doping-less tunnel FET with hetero gate dielectric for enhancement of analog/RF performance

2017 ◽  
Vol 38 (2) ◽  
pp. 024001 ◽  
Author(s):  
Sunny Anand ◽  
R. K. Sarin
Keyword(s):  
Gate Dielectric ◽  
Tunnel Fet ◽  
Rf Performance ◽  
Dual Material

scholarly journals Design and Investigation of F-Shaped Tunnel FET With Enhanced Analog/RF Parameters

2021 ◽  
Author(s):  
PRABHAT SINGH ◽  
DHARMENDRA SINGH YADAV
Keyword(s):  
Electric Field ◽  
Gate Dielectric ◽  
Field Variation ◽  
Current Ratio ◽  
Turn On ◽  
Effective Change ◽  
Tunnel Fet ◽  
Electric Field Variation ◽  
Rf Performance ◽  
Ambipolar Conduction

Abstract In this manuscript, a novel physically doped single gate F-shaped tunnel FET is simulated and optimized. The designed configuration is well optimized and analyzed for different source thickness, source length, drain length with different lateral tunneling lengths between the source edge and gate dielectric. Also, we optimized some stand-points like threshold voltage, ION to IOFF current ratio, ambipolar conduction range, subthreshold swing and various capacitance to rectify the analog/RF performance of single gate F-shaped TFET. Regarding this, we concurrently optimize the lateral tunneling length between source and gate with optimization of source thickness. The variation in lateral tunneling length, the potential and strength of electric field at fixed Vgs voltage is varied which leads to effective change in the ON-current, average sub-threshold swing, and turn ON-voltage. Another side, as well as the source thickness vary, the electric field variation takes place near the edge of source, which leads to variation in the ON-current and ON-voltage. The performance parameters of single gate F-TFET is compared with single gate L-TFET, which is the incentive of this submitted work. The optimized single gate F-TFET have 0.30 V turn ON-voltage with 7.4 mV/decade average sub-threshold swing and high Ion/Ioff ratio approx 1013. Besides, a significant reduction in parasitic capacitance is beneficial to enhanced RF performance with better controllability on channel.

scholarly journals Ambipolar Current Suppression, Analog/RF and Linearity Performance Improvement of Dual Material Stacked Gate Oxide TFET with Dielectric Pocket

2021 ◽  
Author(s):  
dharmender nishad ◽  
kaushal Nigam
Keyword(s):  
Gate Dielectric ◽  
Rf Circuits ◽  
Gate Oxide ◽  
High K ◽  
Ambipolar Current ◽  
High K Dielectric ◽  
Rf Performance ◽  
The Impact ◽  
Dual Material ◽  
Low K

Abstract In this article, the impact of high-K and low-K dielectric pockets on DC, analog/RF, and linearity performance parameters of dual material stacked gate oxide-dielectric pocket-tunnel field-effect transistor (DMSGO-DP-TFET) is investigated. In this regard, a stacked gate oxide (SiO2 + HfO2) with workfunction engineering is taken into consideration to improve the ON-state current (ION ), and suppress the ambipolar current (Iamb). To further improve the performance of the device, a high-K dielectric pocket (HfO2) is used at the drain-channel interface to suppress the Iamb, and at the source-channel interface a low-K dielectric pocket is used to improve the ION and analog/RF performance. Moreover, length of stacked gate segments (L1, L2, L3), pocket height, and thickness are optimized to attain better ION /IOFF ratio, and suppress the Iamb which helps to achieve higher gain and design of analog/RF circuits. The DMSGO-DP-TFET outperforms the dual material control gate-dielectric pocket-TFET (DMCG-DP-TFET) with SiO2 gate oxide and shows increment in ION /IOFF (∼ 4.23 times), 84 % increment in transconductance (gm), 136 % increment in cut-off frequency (fT ), 126 % increment in gain-bandwidth-product (GBP), and better linearity performance parametrs such as gm2 ,gm3, VIP2, VIP3 and IIP3 making the proposed device useful for low power and radio frequency applications.

Comparative analysis of full-gate and short-gate dielectric modulated electrically doped Tunnel-FET based biosensors

2017 ◽  
Vol 111 ◽  
pp. 767-775 ◽  
Author(s):  
Dheeraj Sharma ◽  
Deepika Singh ◽  
Sunil Pandey ◽  
Shivendra Yadav ◽  
P.N. Kondekar
Keyword(s):  
Comparative Analysis ◽  
Gate Dielectric ◽  
Tunnel Fet

scholarly journals Design and Investigation of a Dual Material Gate Arsenic Alloy Heterostructure Junctionless TFET with a Lightly Doped Source

2019 ◽  
Vol 9 (19) ◽  
pp. 4104 ◽  
Author(s):  
Haiwu Xie ◽  
Hongxia Liu ◽  
Shupeng Chen ◽  
Tao Han ◽  
Shulong Wang
Keyword(s):  
Integrated Circuit ◽  
Lattice Mismatch ◽  
Ultra Low Power ◽  
Maximum Cut ◽  
Novel Structure ◽  
Power Integrated Circuit ◽  
Polarization Electric Field ◽  
Source Voltage ◽  
Rf Performance ◽  
Dual Material

This paper designs and investigates a novel structure of dual material gate-engineered heterostructure junctionless tunnel field-effect transistor (DMGE-HJLTFET) with a lightly doped source. Similar to the conventional HJLTFET, the proposed structure still adopts an InAs/GaAs0.1Sb0.9 heterojunction at source and channel interface and employs a polarization electric field at the arsenic heterojunction induced by the lattice mismatch in the InAs and GaAs0.1Sb0.9 zinc blende crystal to improve band to band tunneling (BTBT) current. However, the gate electrode is divided into three parts in DMGE-HJLTFET namely the auxiliary gate (M1), control gate (M2) and tunnel gate (M3) with workfunctions ΦM1, ΦM2 and ΦM3, where ΦM1 = ΦM3 < ΦM2, which not only improves ON-state current but also decreases the OFF-state current. In addition, a lightly doped source is used to further decrease the OFF-state current of this device. Simulation results indicate that DMGE-HJLTFET provides superior metrics in terms of logic and analog/radio frequency (RF) performance as compared with conventional HJLTFET, the maximum ON-state current and transconductance of the DMGE-HJLTFET increases up to 5.46 × 10−4 A/μm and 1.51 × 10−3 S/μm at 1.0 V drain-to-source voltage (Vds). Moreover, average subthreshold swing (SSave) of DMGE-HJLTFET is as low as 15.4 mV/Dec at low drain voltages. Also, DMGE-HJLTFET could achieve a maximum cut-off frequency (fT) of 423 GHz at 0.92 V gate-to-source voltage (Vgs) and a maximum gain bandwidth (GBW) of 82 GHz at Vgs = 0.88 V, respectively. Therefore, it has great potential in future ultra-low power integrated circuit applications.

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