scholarly journals Graph-Based Detection and LDPC Decoding over 2D Intersymbol Interference Channels

2021 ◽  
pp. 91-98
Author(s):  
Yingying Li ◽  
◽  
Zhiliang Qin ◽  
Lianghui Zou ◽  
Yu Qin ◽  
...  
Keyword(s):  
Intersymbol Interference ◽  
Iterative Detection ◽  
Interference Channels ◽  
Parity Check ◽  
Ldpc Decoder ◽  
Ldpc Decoding ◽  
Low Density Parity Check ◽  
Iterative Detection And Decoding ◽  
Check Node ◽  
Isi Channels

In this paper, we propose a fully graph-based iterative detection and decoding scheme for Low-Density Parity-Check (LDPC) coded generalized two-dimensional (2D) intersymbol interference (ISI) channels. The 2D detector consists of a downtrack detector based on the symbol-level sum-product algorithm (SPA) and a bit-level SPA-based crosstrack detector. A LDPC decoder based on simplified check node operations is also proposed to provide soft information for the 2D channel detector. Numerical results show that the proposed receiver achieves better performance as compared with the trellis-based BCJR detector over 2×2 2D channels while at a significantly lower computational complexity.

scholarly journals Reduced-complexity offset min-sum check node unit for layered 5G LDPC decoder

2021 ◽  
Vol 13 (1) ◽  
pp. 7-12
Author(s):  
Vladimir Petrović ◽  
Mezeni El
Keyword(s):  
Parity Check ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Novel Approach ◽  
New Radio ◽  
Variable Weight ◽  
Decoder Architecture ◽  
Check Node ◽  
Higher Weights ◽  
Reduced Complexity

This paper presents a novel approach for the reduced-complexity Min-Sum (MS) decoding of low density parity check (LDPC) codes in the partially parallel layered decoder architecture, which contains a large number of serial check node processors. Reduced complexity is obtained by using the variant of the single-minimum Offset Min-Sum (smOMS) algorithm that approximates a second minimum with the addition of the variable weight parameter to the minimum value. Although the reduced-complexity MS algorithms primarily reduce hardware resources in fully parallel implementations, the results showed that a considerable reduction can be obtained if serial check node processors are used. The paper also proposes a better subminimum estimation for irregular codes from 5G new radio (5G NR). The method uses smaller subminimum estimation weights in check nodes with a higher degree and higher weights in check nodes with a smaller degree, which leads to the significant improvement in the SNR performance. Additionally, it is shown that SNR performance can be further improved by applying offset before minimum calculation, which differs from conventional Min-Sum approaches.

scholarly journals Hardwarearchitektur für einen universellen LDPC Decoder

2009 ◽  
Vol 7 ◽  
pp. 213-218
Author(s):  
C. Beuschel ◽  
H.-J. Pfleiderer
Keyword(s):  
Ldpc Code ◽  
Low Density ◽  
Parity Check ◽  
Wird Eine ◽  
Ldpc Decoder ◽  
Low Density Parity Check

Abstract. Im vorliegenden Beitrag wird eine universelle Decoderarchitektur für einen Low-Density Parity-Check (LDPC) Code Decoder vorgestellt. Anders als bei den in der Literatur häufig beschriebenen Architekturen für strukturierte Codes ist die hier vorgestellte Architektur frei programmierbar, so dass jeder beliebige LDPC Code durch eine Änderung der Initialisierung des Speichers für die Prüfmatrix mit derselben Hardware decodiert werden kann. Die größte Herausforderung beim Entwurf von teilparallelen LDPC Decoder Architekturen liegt im konfliktfreien Datenaustausch zwischen mehreren parallelen Speichern und Berechnungseinheiten, wozu ein Mapping und Scheduling Algorithmus benötigt wird. Der hier vorgestellte Algorithmus stützt sich auf Graphentheorie und findet für jeden beliebigen LDPC Code eine für die Architektur optimale Lösung. Damit sind keine Wartezyklen notwendig und die Parallelität der Architektur wird zu jedem Zeitpunkt voll ausgenutzt.

An Efficient VLSI Architecture for Nonbinary LDPC Decoder with Adaptive Message Control

2015 ◽  
Vol 4 (1) ◽  
pp. 6
Author(s):  
Varatharajan Ramachandran
Keyword(s):  
Power Consumption ◽  
Vlsi Architecture ◽  
Ldpc Codes ◽  
Parity Check ◽  
Decoding Complexity ◽  
Ldpc Decoder ◽  
Message Length ◽  
Low Density Parity Check ◽  
Decoder Architecture ◽  
Memory Accesses

<p>A new decoder architecture for nonbinary low-density parity check (LDPC) codes is presented in this paper to reduce the hardware operational complexity and power consumption. Adaptive message control (AMC) is to achieve the low decoding complexity,  that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. A new horizontal nonbinary LDPC decoder architecture is developed to implement AMC. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation.</p>

Reduced decoding time of LDPC code using convolutional code with Vitrebi decoding in Underwater Communication

2018 ◽  
Vol 7 (2.25) ◽  
pp. 167
Author(s):  
Krishnamoorthy N.R ◽  
Ramadevi R ◽  
Marshiana M ◽  
Sujatha Kumaran
Keyword(s):  
No Value ◽  
Convolutional Code ◽  
Ldpc Code ◽  
Code Rate ◽  
Underwater Communication ◽  
Parity Check ◽  
Minimal Error ◽  
Ldpc Decoding ◽  
Low Density Parity Check ◽  
High Code Rate

Low Density Parity Check code is the more efficient technique to attain the minimal error rate in the underwater channel. To reduce the processing delay in the LDPC decoding, convolutional code with high code rate is used. The result showed that the BER of 10-4 can be obtained with Eb/No value of 20 for code rate of ½ and 12 for code rate of 1/8. It is also showed in result that the decoding time is reduced one-third for data size of 500 and one-tenth for the data size of 1500 bits.  

Iterative Detection and Decoding for TDMR With 2-D Intersymbol Interference Using the Four-Rectangular-Grain Model

2015 ◽  
Vol 51 (7) ◽  
pp. 1-12 ◽  
Author(s):  
Michael Carosino ◽  
Jiyang Yu ◽  
Yiming Chen ◽  
Morteza Mehrnoush ◽  
Benjamin J. Belzer ◽  
...  
Keyword(s):  
Intersymbol Interference ◽  
Iterative Detection ◽  
Iterative Detection And Decoding ◽  
Grain Model

scholarly journals Conception of a new LDPC decoder with hardware implementation on FPGA card

2014 ◽  
Vol 3 (4) ◽  
pp. 451
Author(s):  
Anas El habti El idrissi ◽  
Rachid El Gouri ◽  
Hlou Laamari
Keyword(s):  
Error Detection ◽  
Matrix Equation ◽  
Coding Theory ◽  
Ldpc Codes ◽  
Low Density ◽  
Parity Check ◽  
Fast Encoding ◽  
Ldpc Decoder ◽  
Low Density Parity Check ◽  
Simplified Algorithm

Low Density Parity-Check codes are one of the hottest topics in coding theory nowadays. Equipped with very fast encoding and decoding algorithms, LDPC codes are very attractive both theoretically and practically. In this paper, A simplified algorithm for decoding Low-Density Parity-Check (LDPC) codes is proposed with a view to reduce the implementation complexity, this algorithm is based on a simple matrix equation which must be resolved in order to calculate all possible solutions of this equation, and then a simple circuit will be used to determine the errors produced during the transmission channel. First, we developed the design of the proposed algorithm second, we generated and simulated the hardware description language source code using Quartus software tools and finally we implemented the new algorithm of LDPC codes on FPGA card. Keywords: Bit-Flipping Algorithm, Error Detection, FPGA Card, LDPC Decoder, Matrix Equation.

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