A Compact Model for Dual Material Gate Stack (DUMGAS) Fully Depleted SOI MOSFET

2013 ◽  
Vol 10 (13) ◽  
pp. 4233-4245
Author(s):  
Changyong Zheng
Keyword(s):  
Compact Model ◽  
Gate Stack ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Dual Material

scholarly journals 2-D analytical modeling of dual material gate fully depleted SOI MOSFET with high-k dielectric

2008 ◽  
Vol 57 (6) ◽  
pp. 3807
Author(s):  
Luan Su-Zhen ◽  
Liu Hong-Xia ◽  
Jia Ren-Xu ◽  
Cai Nai-Qiong
Keyword(s):  
Analytical Modeling ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
High K ◽  
High K Dielectric ◽  
Dual Material

Completely Surface-Potential-Based Compact Model of the Fully Depleted SOI-MOSFET Including Short-Channel Effects

2006 ◽  
Vol 53 (9) ◽  
pp. 2017-2024 ◽  
Author(s):  
N. Sadachika ◽  
D. Kitamaru ◽  
Y. Uetsuji ◽  
D. Navarro ◽  
M.M. Yusoff ◽  
...  
Keyword(s):  
Surface Potential ◽  
Compact Model ◽  
Short Channel Effects ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Channel Effects

scholarly journals Analytical Modeling and Simulation of Nanoscale Fully Depleted Dual Metal Gate SOI MOSFET

2019 ◽  
Vol 8 (10) ◽  
pp. 2946-2950
Keyword(s):  
Analytical Modeling ◽  
Cmos Technology ◽  
Step Function ◽  
Device Structure ◽  
Short Channel ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
New Device ◽  
Dual Metal ◽  
Dual Material

The demand and development of scaled semiconductors devices for upcoming challenges in VLSI technology is unending. CMOS technology plays a very important role in fulfilling this criterion. The conventional MOSFET exhibits short channel effects (SCE) and performance degradation when scaled down in the nanometer regime. In order to meet the required enhanced performance and to further increase the device density new materials and new device structures have been developed. This paper analyses the performance characteristics of one of such improved device structure i.e Fully Depleted Silicon over Insulator (FDSOI) which also incorporate the gate having two metals of different work function specifically called Dual Material Gate (DMG) SOI MOSFET. The analytical modeling for this device structure has also been carried out. The simulation characteristics match closely with analytical results and as the surface potential profile of the device has step function in ensures that this device effectively reduces the SCE.

Modeling of Doping Effects in Surface Potential Based Compact Model of Fully Depleted SOI MOSFET

2021 ◽  
Author(s):  
Sebastien Martinie ◽  
Olivier Rozeau ◽  
Plamen Kolev ◽  
Patrick Scheer ◽  
Salim El Ghouli ◽  
...  
Keyword(s):  
Surface Potential ◽  
Compact Model ◽  
Fully Depleted ◽  
Soi Mosfet ◽  
Doping Effects

Performance Analysis of Gate-Stack Dual-Material DG MOSFET Using Work-Function Modulation Technique for Lower Technology Nodes

Silicon ◽  
2021 ◽  
Author(s):  
Satish K. Das ◽  
Umakanta Nanda ◽  
Sudhansu M. Biswal ◽  
Chandan Kumar Pandey ◽  
Lalat Indu Giri
Keyword(s):  
Performance Analysis ◽  
Work Function ◽  
Gate Stack ◽  
Modulation Technique ◽  
Dg Mosfet ◽  
Technology Nodes ◽  
Dual Material
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