Monolithically Integrated Ring Resonator Systems On-chip

Предлагаются методы построения платформ прототипирования высокопроизводительных систем на кристалле для задач искусственного интеллекта. Изложены требования к платформам подобного класса и принципы изменения проекта СнК для имплементации в прототип. Рассматриваются методы отладки проектов на платформе прототипирования. Приведены результаты работ алгоритмов компьютерного зрения с использованием нейросетевых технологий на FPGA-прототипе семантических ядер ELcore. Methods have been proposed for building prototyping platforms for high-performance systems-on-chip for artificial intelligence tasks. The requirements for platforms of this class and the principles for changing the design of the SoC for implementation in the prototype have been described as well as methods of debugging projects on the prototyping platform. The results of the work of computer vision algorithms using neural network technologies on the FPGA prototype of the ELcore semantic cores have been presented.

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A Survey of Software-Defined Networks-on-Chip: Motivations, Challenges and Opportunities

Micromachines ◽

10.3390/mi12020183 ◽

2021 ◽

Vol 12 (2) ◽

pp. 183

Author(s):

Jose Ricardo Gomez-Rodriguez ◽

Remberto Sandoval-Arechiga ◽

Salvador Ibarra-Delgado ◽

Viktor Ivan Rodriguez-Abdala ◽

Jose Luis Vazquez-Avila ◽

...

Keyword(s):

Single Chip ◽

Synthesis Time ◽

Networks On Chip ◽

Data Dependencies ◽

Layered Architecture ◽

Systems On Chip ◽

Challenges And Opportunities ◽

Computing Platforms ◽

On Chip ◽

Many Core

Current computing platforms encourage the integration of thousands of processing cores, and their interconnections, into a single chip. Mobile smartphones, IoT, embedded devices, desktops, and data centers use Many-Core Systems-on-Chip (SoCs) to exploit their compute power and parallelism to meet the dynamic workload requirements. Networks-on-Chip (NoCs) lead to scalable connectivity for diverse applications with distinct traffic patterns and data dependencies. However, when the system executes various applications in traditional NoCs—optimized and fixed at synthesis time—the interconnection nonconformity with the different applications’ requirements generates limitations in the performance. In the literature, NoC designs embraced the Software-Defined Networking (SDN) strategy to evolve into an adaptable interconnection solution for future chips. However, the works surveyed implement a partial Software-Defined Network-on-Chip (SDNoC) approach, leaving aside the SDN layered architecture that brings interoperability in conventional networking. This paper explores the SDNoC literature and classifies it regarding the desired SDN features that each work presents. Then, we described the challenges and opportunities detected from the literature survey. Moreover, we explain the motivation for an SDNoC approach, and we expose both SDN and SDNoC concepts and architectures. We observe that works in the literature employed an uncomplete layered SDNoC approach. This fact creates various fertile areas in the SDNoC architecture where researchers may contribute to Many-Core SoCs designs.

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A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization

Micromachines ◽

10.3390/mi12010082 ◽

2021 ◽

Vol 12 (1) ◽

pp. 82

Author(s):

Rafel Perelló-Roig ◽

Jaume Verd ◽

Sebastià Bota ◽

Jaume Segura

Keyword(s):

Cmos Technology ◽

Open Loop ◽

Transimpedance Amplifier ◽

Mems Devices ◽

Monolithically Integrated ◽

Mems Resonators ◽

Electromechanical Performance ◽

Cmos Mems ◽

Promising Solution ◽

On Chip

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-µm CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2—input-referred current noise of 192 fA/Hz1/2—at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance—mostly associated with the MEMS layout—representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

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