Impact-Based Area Allocation for Yield Optimization in Integrated Circuits

2016 ◽  
Vol 1 (6) ◽  
Author(s):  
Billion Abraham ◽  
Arif Widodo ◽  
Poki Chen
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Current Steering ◽  
Yield Optimization ◽  
Digital To Analog Converter ◽  
Integral Nonlinearity ◽  
Analog Converter ◽  
Layout Area ◽  
Binary Weighted ◽  
The Impact

Abstract In analog integrated circuit (IC) layout, area allocation is a very important issue for achieving good mismatch cancellation. However, most IC layout papers focus only on layout strategy to reduce systematic mismatch. In 2006, an outstanding paper presenting area allocation strategy was published to introduce technique for random mismatch reduction. Instead of using general theoretical study to prove the strategy, this research presented close-to-optimum simulations only on case-bycase basis. The impact-based area allocation for yield optimization in integrated circuits is proposed in this chapter. To demonstrate the corresponding strategy, not only a theoretical analysis but also an integral nonlinearity-based yield simulation will be given to derive optimum area allocation for binary weighted current steering digital-to-analog converter (DAC). The result will be concluded to convince IC designers how to allocate area for critical devices in an optimum way.

Processing and Prolonged 500 °C Testing of 4H-SiC JFET Integrated Circuits with Two Levels of Metal Interconnect

2016 ◽  
Vol 858 ◽  
pp. 908-912 ◽  
Author(s):  
David J. Spry ◽  
Philip G. Neudeck ◽  
Liang Yu Chen ◽  
Dorothy Lukco ◽  
Carl W. Chang ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Field Effect Transistor ◽  
Electrical Power ◽  
Random Access ◽  
Memory Cell ◽  
Access Memory ◽  
Digital To Analog Converter ◽  
Analog Converter ◽  
Effect Transistor

Complex integrated circuit (IC) chips rely on more than one level of interconnect metallization for routing of electrical power and signals. This work reports the processing and testing of 4H-SiC junction field effect transistor (JFET) prototype IC’s with two levels of metal interconnect capable of prolonged operation at 500 °C. Packaged functional circuits including 3- and 11-stage ring oscillators, a 4-bit digital to analog converter, and a 4-bit address decoder and random access memory cell have been demonstrated at 500 °C. A 3-stage oscillator functioned for over 3000 hours at 500 °C in air ambient. Improved reproducibility remains to be accomplished.

Analyzing the Impact of X-Ray Tomography on the Reliability of Integrated Circuits

2015 ◽  
Author(s):  
Halit Dogan ◽  
Md Mahbub Alam ◽  
Navid Asadizanjani ◽  
Sina Shahbazmohamadi ◽  
Domenic Forte ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
3D Imaging ◽  
Three Dimensional ◽  
Serial Sectioning ◽  
Promising Technique ◽  
Flash Memories ◽  
X Ray ◽  
3D Information ◽  
The Impact

Abstract X-ray tomography is a promising technique that can provide micron level, internal structure, and three dimensional (3D) information of an integrated circuit (IC) component without the need for serial sectioning or decapsulation. This is especially useful for counterfeit IC detection as demonstrated by recent work. Although the components remain physically intact during tomography, the effect of radiation on the electrical functionality is not yet fully investigated. In this paper we analyze the impact of X-ray tomography on the reliability of ICs with different fabrication technologies. We perform a 3D imaging using an advanced X-ray machine on Intel flash memories, Macronix flash memories, Xilinx Spartan 3 and Spartan 6 FPGAs. Electrical functionalities are then tested in a systematic procedure after each round of tomography to estimate the impact of X-ray on Flash erase time, read margin, and program operation, and the frequencies of ring oscillators in the FPGAs. A major finding is that erase times for flash memories of older technology are significantly degraded when exposed to tomography, eventually resulting in failure. However, the flash and Xilinx FPGAs of newer technologies seem less sensitive to tomography, as only minor degradations are observed. Further, we did not identify permanent failures for any chips in the time needed to perform tomography for counterfeit detection (approximately 2 hours).

Low-power 8-bit 5-GS/s digital-to-analog converter for multi-gigabit wireless transceivers

2012 ◽  
Vol 4 (3) ◽  
pp. 275-282 ◽  
Author(s):  
Behnam Sedighi ◽  
Mahdi Khafaji ◽  
Johann Christoph Scheytt
Keyword(s):  
Low Power ◽  
High Speed ◽  
Wireless Transceivers ◽  
Digital To Analog Converter ◽  
Bicmos Technology ◽  
Analog Converter ◽  
Sige Bicmos ◽  
Digital To Analog ◽  
On Chip ◽  
Binary Weighted

We present a method to realize a low-power and high-speed digital-to-analog converter (DAC) for system-on-chip applications. The new method is a combination of binary-weighted current cells and R-2R ladder and is specially suited for modern BiCMOS technologies. A prototype 5 GS/s DAC is implemented in 0.13 μm SiGe BiCMOS technology. The DAC dissipates 26 mW and provides an SFDR higher than 48 dB for output frequencies up to 1 GHz.

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