Degradation of SiC High-Voltage pin Diodes

MRS Bulletin ◽  
2005 ◽  
Vol 30 (4) ◽  
pp. 305-307 ◽  
Author(s):  
Seoyong Ha ◽  
J. P. Bergman
Keyword(s):  
Basal Plane ◽  
Current Flow ◽  
Power Devices ◽  
Device Structure ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Partial Dislocations ◽  
Nucleation Sites ◽  
Fundamental Understanding ◽  
Voltage Degradation

AbstractThe recent discovery of forward-voltage degradation in SiC pin diodes has created an obstacle to the successful commercialization of SiC bipolar power devices. Accordingly, it has attracted intense interest around the world. This article summarizes the progress in both the fundamental understanding of the problem and its elimination.The degradation is due to the formation of Shockley-type stacking faults in the drift layer, which occurs through glide of bounding partial dislocations. The faults gradually cover the diode area, impeding current flow. Since the minimization of stress in the device structure could not prevent this phenomenon, its driving force appears to be intrinsic to the material. Stable devices can be fabricated by eliminating the nucleation sites, namely, dissociated basal-plane dislocations in the drift layer.Their density can be reduced by the conversion of basal-plane dislocations propagating from the substrate into threading dislocations during homoepitaxy.

Comparative Evaluation of Forward Voltage Degradation due to Propagating and Converted Basal Plane Dislocations

2018 ◽  
Vol 924 ◽  
pp. 143-146 ◽  
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Strong Correlation ◽  
Basal Plane ◽  
Comparative Evaluation ◽  
Epitaxial Layers ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Forward Current ◽  
Voltage Degradation ◽  
The Relationship ◽  
Drift Layer

This study investigated the relationship between the forward voltage degradation induced by SSF expansion and (a) BPD density in substrates and epitaxial layers of SiC, and (b) the temperature during the application forward current to the pin diodes. The Vf shift caused by the BPDs in the drift layer simply depended on the BPD density. However, no correlation was initially observed between the Vf shift and BPD density in the substrate; instead a strong correlation was observed between the Vf shift and the device temperature measured when applying the current stress. Thus when we selected samples which show the same temperature at that time, a correlation was observed between the Vf shift and the BPD density in the SiC substrate, with the slope corresponding to the former, drift layer relationship. Therefore, due to the high BPD density in the SiC substrate, suppressing the Vf shift due to BPD density in this region is highly important, and a combination of approaches is therefore proposed in order to reduce the overall forward voltage degradation.

Effect of Stacking Faults Originating from Half Loop Arrays on Electrical Behavior of 10 kV 4H-SiC PiN Diodes

2012 ◽  
Vol 717-720 ◽  
pp. 387-390 ◽  
Author(s):  
Robert E. Stahlbush ◽  
Qing Chun Jon Zhang ◽  
Anant K. Agarwal ◽  
Nadeemullah A. Mahadik
Keyword(s):  
Basal Plane ◽  
Forward Bias ◽  
Stacking Faults ◽  
Device Fabrication ◽  
Electrical Behavior ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Electrical Stress ◽  
Half Loop

The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm2, and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

Detecting Basal Plane Dislocations Converted in Highly Doped Epilayers

2019 ◽  
Vol 963 ◽  
pp. 272-275
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Silicon Carbide ◽  
Basal Plane ◽  
Near Infrared ◽  
Minority Carrier ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Near Ultraviolet ◽  
Bipolar Devices ◽  
Voltage Degradation

Suppression of the forward voltage degradation is essential in fabricating bipolar devices on silicon carbide. Using a highly N–doped 4H–epilayer as an enhancing minority carrier recombination layer is a powerful tool for reducing the expansion of BPDs converted at the epi/sub interface; however, these BPDs cannot be observed by using the near–infrared photoluminescence in the layer. Near–ultraviolet photoluminescence was instead used to detect BPDs as dark lines. In addition, a short BPD converted near the epi/sub interface and contributing to the degradation was detected. When this evaluation was applied to the fabrication of a pin diode including a highly N–doped 4H–epilayer, the Vf shift was suppressed in comparison with that in a diode without the layer.

Mechanisms of Stacking Fault Growth in SiC PiN Diodes

2004 ◽  
Vol 815 ◽  
Author(s):  
R. E. Stahlbush ◽  
M. E. Twigg ◽  
J. J. Sumakeris ◽  
K. G. Irvine ◽  
P. A. Losee
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Stacking Fault ◽  
Drift Region ◽  
Pin Diodes ◽  
Current Time ◽  
Partial Dislocations ◽  
Initial Evolution ◽  
A Chain ◽  
Fault Growth

AbstractThe early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.

Performance of Silicon Carbide PiN Diodes Fabricated on Basal Plane Dislocation-Free Epilayers

2006 ◽  
Vol 527-529 ◽  
pp. 371-374 ◽  
Author(s):  
Ze Hong Zhang ◽  
A.E. Grekov ◽  
Priyamvada Sadagopan ◽  
S.I. Maximenko ◽  
Tangali S. Sudarshan
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Surface Damage ◽  
Induced Current ◽  
Pin Diodes ◽  
Current Stressing ◽  
Forward Current ◽  
Nucleation Sites ◽  
Basal Plane Dislocation ◽  
Electron Beam Induced Current

The nucleation sites of stacking faults (SFs) during forward current stress operation of 4H-SiC PiN diodes were investigated by the electron beam induced current (EBIC) mode of scanning electron microscopy (SEM), and the primary SF nucleation sites were found to be basal plane dislocations (BPDs). Damage created on the diode surface also acts as SF nucleation sites. By using a novel BPD-free SiC epilayer, and avoiding surface damage, PiN diodes were fabricated which did not exhibit SF formation under current stressing at 200A/cm2 for 3 hours.

Propagation of Current-Induced Stacking Faults and Forward Voltage Degradation in 4H-SiC PiN Diodes

2002 ◽  
Vol 389-393 ◽  
pp. 427-430 ◽  
Author(s):  
Robert E. Stahlbush ◽  
Jeffery B. Fedison ◽  
Steve Arthur ◽  
L.B. Rowland ◽  
James W. Kretchmer ◽  
...  
Keyword(s):  
Stacking Faults ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Voltage Degradation

Status of 4H-SiC Substrate and Epitaxial Materials for Commercial Power Applications

2004 ◽  
Vol 815 ◽  
Author(s):  
A.R. Powell ◽  
J.J. Sumakeris ◽  
R.T. Leonard ◽  
M.F. Brady ◽  
St.G. Müller ◽  
...  
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Epitaxial Layers ◽  
Power Devices ◽  
Pin Diodes ◽  
Dislocation Densities ◽  
The Status ◽  
Basal Plane Dislocation ◽  
Current Production ◽  
Schottky Device

AbstractThe performance enhancements offered by the next generation of SiC high power devices offer potential for enormous growth in SiC power device markets in the next few years. For this growth to occur, it is imperative that substrate and epitaxial material quality increases to meet the needs of the targeted applications. We will discuss the status and requirements for SiC substrates and epitaxial material for power devices such as Schottky and PiN diodes. For the SiC Schottky device where current production is approaching 50 amp devices, there are several material aspects that are key. These include; wafer diameter (3-inch and 100-mm), micropipe density (<0.3 cm−2 for 3-inch substrates and 16 cm−2 for 100-mm substrates), epitaxial defect densities (total electrically active defects <1.5 cm−2), epitaxial doping and epitaxial thickness uniformity. For the PiN diodes the major challenge is the degradation of the Vf characteristics due to the introduction of stacking faults during the device operation. We have demonstrated that the stacking faults are often generated from basal plane dislocations in the active region of the device. Additionally we have demonstrated that by reducing the basal plane dislocation density, stable PiN diodes can be produced. At present typical basal plane dislocation densities in our epitaxial layers are 100 to 500 cm−2; however, we have achieved basal plane dislocation densities as low as 4 cm−2 in epitaxial layers grown on 8° off-axis 4H-SiC substrates.

Development of High-Voltage 4H-SiC PiN Diodes on 4° and 8° Off-Axis Substrates

2013 ◽  
Vol 740-742 ◽  
pp. 907-910 ◽  
Author(s):  
Dai Okamoto ◽  
Yasunori Tanaka ◽  
Norio Matsumoto ◽  
Makoto Mizukami ◽  
Chiharu Ota ◽  
...  
Keyword(s):  
Electrical Properties ◽  
High Voltage ◽  
Avalanche Breakdown ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Small Test ◽  
Voltage Degradation

13-kV 4H-SiC PiN diodes were fabricated on 4° and 8° off-axis substrates and their electrical properties were examined. Small test PiN diodes with various JTE concentrations were fabricated and the dependence of JTE concentration was examined. The highest breakdown voltages were 14.6 and 14.1 kV at a JTE1 concentration of 1.9 × 1017 cm−3 for both the 4° and 8° off-axis substrates. Based on the results, 4 mm × 4 mm SiC PiN diodes were successfully fabricated and exhibited avalanche breakdown voltages of 14.0 and 13.5 kV for the 4° and 8° off-axis substrates, respectively. Forward voltage degradation was larger for the 8° off-axis substrates.

scholarly journals Forward Voltage Degradation of 4H-SiC pin Diodes and High Voltage 4H-SiC pin Diodes on the (000-1) C-Face with Reduced Forward Degradation

2008 ◽  
Vol 128 (8) ◽  
pp. 1013-1019 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
Ryosuke Ishii ◽  
Hidekazu Tsuchida ◽  
Toshiyuku Miyanagi ◽  
...  
Keyword(s):  
High Voltage ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Voltage Degradation

Growth of Low Basal Plane Dislocation Density SiC Epitaxial Layers

2006 ◽  
Vol 527-529 ◽  
pp. 243-246 ◽  
Author(s):  
Ze Hong Zhang ◽  
Tangali S. Sudarshan
Keyword(s):  
Dislocation Density ◽  
Epitaxial Growth ◽  
Basal Plane ◽  
Voltage Drop ◽  
Etch Pits ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Forward Voltage Drop ◽  
Basal Plane Dislocation ◽  
Edge Dislocations

A method was developed in our laboratory to grow low basal plane dislocation (BPD) density and BPD-free SiC epilayers. The key approach is to subject the SiC substrates to defect preferential etching, followed by conventional epitaxial growth. It was found that the creation of BPD etch pits on the substrates can greatly enhance the conversion of BPDs to threading edge dislocations (TEDs) during epitaxy, and thus low BPD density and BPD-free SiC epilayers are obtained. The reason why BPD etch pits can promote the above conversion is discussed. The SiC epilayer growth by this method is very promising in overcoming forward voltage drop degradation of SiC PiN diodes.

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