Detecting Basal Plane Dislocations Converted in Highly Doped Epilayers

2019 ◽  
Vol 963 ◽  
pp. 272-275
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Silicon Carbide ◽  
Basal Plane ◽  
Near Infrared ◽  
Minority Carrier ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Near Ultraviolet ◽  
Bipolar Devices ◽  
Voltage Degradation

Suppression of the forward voltage degradation is essential in fabricating bipolar devices on silicon carbide. Using a highly N–doped 4H–epilayer as an enhancing minority carrier recombination layer is a powerful tool for reducing the expansion of BPDs converted at the epi/sub interface; however, these BPDs cannot be observed by using the near–infrared photoluminescence in the layer. Near–ultraviolet photoluminescence was instead used to detect BPDs as dark lines. In addition, a short BPD converted near the epi/sub interface and contributing to the degradation was detected. When this evaluation was applied to the fabrication of a pin diode including a highly N–doped 4H–epilayer, the Vf shift was suppressed in comparison with that in a diode without the layer.

Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

2020 ◽  
Vol 1004 ◽  
pp. 439-444
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Field Effect Transistor ◽  
Minority Carrier ◽  
Oxide Semiconductor ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Crucial Problem ◽  
Basal Plane Dislocation ◽  
Effect Transistor ◽  
Voltage Degradation

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

Comparative Evaluation of Forward Voltage Degradation due to Propagating and Converted Basal Plane Dislocations

2018 ◽  
Vol 924 ◽  
pp. 143-146 ◽  
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Strong Correlation ◽  
Basal Plane ◽  
Comparative Evaluation ◽  
Epitaxial Layers ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Forward Current ◽  
Voltage Degradation ◽  
The Relationship ◽  
Drift Layer

This study investigated the relationship between the forward voltage degradation induced by SSF expansion and (a) BPD density in substrates and epitaxial layers of SiC, and (b) the temperature during the application forward current to the pin diodes. The Vf shift caused by the BPDs in the drift layer simply depended on the BPD density. However, no correlation was initially observed between the Vf shift and BPD density in the substrate; instead a strong correlation was observed between the Vf shift and the device temperature measured when applying the current stress. Thus when we selected samples which show the same temperature at that time, a correlation was observed between the Vf shift and the BPD density in the SiC substrate, with the slope corresponding to the former, drift layer relationship. Therefore, due to the high BPD density in the SiC substrate, suppressing the Vf shift due to BPD density in this region is highly important, and a combination of approaches is therefore proposed in order to reduce the overall forward voltage degradation.

Degradation of SiC High-Voltage pin Diodes

MRS Bulletin ◽  
2005 ◽  
Vol 30 (4) ◽  
pp. 305-307 ◽  
Author(s):  
Seoyong Ha ◽  
J. P. Bergman
Keyword(s):  
Basal Plane ◽  
Current Flow ◽  
Power Devices ◽  
Device Structure ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Partial Dislocations ◽  
Nucleation Sites ◽  
Fundamental Understanding ◽  
Voltage Degradation

AbstractThe recent discovery of forward-voltage degradation in SiC pin diodes has created an obstacle to the successful commercialization of SiC bipolar power devices. Accordingly, it has attracted intense interest around the world. This article summarizes the progress in both the fundamental understanding of the problem and its elimination.The degradation is due to the formation of Shockley-type stacking faults in the drift layer, which occurs through glide of bounding partial dislocations. The faults gradually cover the diode area, impeding current flow. Since the minimization of stress in the device structure could not prevent this phenomenon, its driving force appears to be intrinsic to the material. Stable devices can be fabricated by eliminating the nucleation sites, namely, dissociated basal-plane dislocations in the drift layer.Their density can be reduced by the conversion of basal-plane dislocations propagating from the substrate into threading dislocations during homoepitaxy.

Dynamic Characteristics of 4H-SiC pin Diode on (000-1)C-Face with Small Forward Degradation

2006 ◽  
Vol 527-529 ◽  
pp. 1359-1362 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
R. Ishii ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
...  
Keyword(s):  
Dynamic Characteristics ◽  
Stress Test ◽  
Pin Diode ◽  
Forward Voltage ◽  
Current Stress ◽  
Before And After ◽  
Voltage Degradation ◽  
A Current

Forward voltage degradation has been reduced by fabricating diodes on the (000-1)C-face. The reverse recovery characteristics of the 4H-SiC pin diode on the (000-1)C-face have been investigated. The pin diode on the C-face has superior potential to that on the Si-face among all parameters of the reverse recovery characteristics. The pin diode on the Si-face after conducting a current stress test tends to exhibit a fast turn-off as compared with that before conducting the stress test. On the C-face, however, there is little difference in reverse recovery characteristics between before and after conducting the current stress test.

Triangular Single Shockley Stacking Fault Analyses on 4H-SiC PiN Diode with Forward Voltage Degradation

2020 ◽  
Vol 49 (9) ◽  
pp. 5232-5239 ◽  
Author(s):  
Johji Nishio ◽  
Aoi Okada ◽  
Chiharu Ota ◽  
Mitsuhiro Kushibe
Keyword(s):  
Stacking Fault ◽  
Pin Diode ◽  
Forward Voltage ◽  
Voltage Degradation

8.3 kV 4H-SiC PiN Diode on (000-1) C-Face with Small Forward Voltage Degradation

2005 ◽  
pp. 969-972 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
Isaho Kamata ◽  
...  
Keyword(s):  
Pin Diode ◽  
Forward Voltage ◽  
Voltage Degradation

8.3 kV 4H-SiC PiN Diode on (000-1) C-Face with Small Forward Voltage Degradation

2005 ◽  
Vol 483-485 ◽  
pp. 969-972 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
Isaho Kamata ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
High Voltage ◽  
Pin Diode ◽  
Forward Voltage ◽  
Pin Diodes ◽  
High Breakdown Voltage ◽  
Voltage Degradation

The dependence of forward voltage degradation on crystal faces for 4H-SiC pin diodes has been investigated. The forward voltage degradation has been reduced by fabricating the diodes on the (000-1) C-face off-angled toward <11-20>. High-voltage 4H-SiC pin diodes on the (000-1) C-face with small forward voltage degradation have also been fabricated successfully. A high breakdown voltage of 4.6 kV and DVf of 0.04 V were achieved for a (000-1) C-face pin diode. A 8.3 kV blocking performance, which is the highest voltage in the use of (000-1) C-face, is also demonstrated in 4H-SiC pin diode.

Detection of Crystal Defects in High Doped Epitaxial Layers and Substrates by Photoluminescence

2017 ◽  
Vol 897 ◽  
pp. 222-225 ◽  
Author(s):  
Hrishikesh Das ◽  
Swapna Sunkari ◽  
Hans Naas ◽  
Martin Domeij ◽  
Andrei Konstantinov ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Grain Boundaries ◽  
Basal Plane ◽  
Potassium Hydroxide ◽  
Crystal Defects ◽  
Buffer Layers ◽  
Screw Dislocations ◽  
Near Ultraviolet ◽  
Doped Silicon

In this work, the detection and characterization of various crystal defects in high doped silicon carbide by photoluminescence (PL) is explored. The detection of basal plane dislocations in high doped epitaxial buffer layers is demonstrated using the near ultraviolet (NUV) spectra. Several characteristic defects in high doped 150mm substrates like grain boundaries and screw dislocations are also detected and characterized using the NUV PL spectra. Further characterization using molten potassium hydroxide etching is presented.

Cause of Forward Voltage Degradation for 4H-SiC PiN Diode with Additional Process

2014 ◽  
Vol 1635 ◽  
pp. 121-126
Author(s):  
Tetsuro Hemmi ◽  
Koji Nakayama ◽  
Katsunori Asano ◽  
Tetsuya Miyazawa ◽  
Hidekazu Tsuchida
Keyword(s):  
Stress Test ◽  
Process Condition ◽  
Device Fabrication ◽  
Pin Diode ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Half Loop ◽  
Additional Process ◽  
Voltage Degradation ◽  
A Current

ABSTRACTThe forward voltage degradation in 4H-SiC PiN diodes with a simplified process and that in 4H-SiC pin diodes with additional processes are investigated. Photoluminescence images were also observed to identify the cause of forward voltage degradation. The forward voltage degradations of 4H-SiC PiN diodes with additional processes were larger than those with a simplified process. Observing photoluminescence images of diodes after a current stress test showed that less than 25% of Shockley-type stacking faults in 4H-SiC PiN diodes with a simplified process are caused by half-loop dislocations, which are generated not only in the additional processes but also in the whole device fabrication process. With additional processes, those rates are over 65%, which may be reduced by eliminating half-loop dislocations due to the optimization of the process condition and sequence.

An Infrared Microscope for Use on a Focused Ion Beam for Circuit Edit and Backside Edit Applications

2015 ◽  
Author(s):  
Alexander Richards ◽  
Matthew Weschler ◽  
Michael Durller
Keyword(s):  
Focused Ion Beam ◽  
Near Infrared ◽  
Ion Beam ◽  
Visible Spectrum ◽  
Camera System ◽  
Buried Structures ◽  
Ir Camera ◽  
Area Of Interest ◽  
Near Ultraviolet ◽  
Infrared Microscope

Abstract To help solve the navigational problem, i.e., being able to successfully locate a circuit for probing or editing without destroying chip functionality, a near-infrared (NIR), near-ultraviolet (NUV), and visible spectrum camera system was developed that attaches to most focused ion beam (FIB) or scanning electron microscope vacuum chambers. This paper reviews the details of the design and implementation of the NIR/NUV camera system, as instantiated upon the FEI FIB 200, with a particular focus on its use for the visualization of buried structures, and also for non-destructive real time area of interest location and end point detection. It specifically considers the use of the micro-optical camera system for its benefit in assisting with frontside and backside circuit edit, as well as other typical FIB milling activities. The quality of the image obtained by the IR camera rivals or exceeds traditional optical based imaging microscopy techniques.

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