Effect of Stacking Faults Originating from Half Loop Arrays on Electrical Behavior of 10 kV 4H-SiC PiN Diodes

2012 ◽  
Vol 717-720 ◽  
pp. 387-390 ◽  
Author(s):  
Robert E. Stahlbush ◽  
Qing Chun Jon Zhang ◽  
Anant K. Agarwal ◽  
Nadeemullah A. Mahadik
Keyword(s):  
Basal Plane ◽  
Forward Bias ◽  
Stacking Faults ◽  
Device Fabrication ◽  
Electrical Behavior ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Electrical Stress ◽  
Half Loop

The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm2, and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

SXRT Investigations on Electrically Stressed 4H-SiC PiN Diodes for 6.5 kV

2013 ◽  
Vol 740-742 ◽  
pp. 899-902 ◽  
Author(s):  
Birgit Kallinger ◽  
Patrick Berwian ◽  
Jochen Friedrich ◽  
Christian Hecht ◽  
Dethard Peters ◽  
...  
Keyword(s):  
Stress Test ◽  
Stacking Faults ◽  
Active Area ◽  
Structural Defects ◽  
Electrical Characteristics ◽  
Wafer Level ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Electrical Stress ◽  
Voltage Drift

4H-SiC PiN diodes for 6.5 kV were manufactured on both 4° and 8° off-cut substrates and subjected to an electrical stress test on wafer level and subsequent analysis of structural defects present in the active area of the diodes. For 8° off-cut diodes, the electrical characteristics with respect to leakage current and forward voltage drift are worse than the electrical characteristics of 4° off-cut diodes. Furthermore, a large number of stacking faults was found in 8° off-cut diodes, but little evidence for bipolar degradation was found in 4° off-cut diodes. Therefore, bipolar degradation was significantly reduced by avoiding BPDs in the active area of PiN diodes, i.e. by the use of 4° off-cut substrates. Furthermore, a strong correlation was found between the electrical screening test on wafer level and critical defects.

Cause of Forward Voltage Degradation for 4H-SiC PiN Diode with Additional Process

2014 ◽  
Vol 1635 ◽  
pp. 121-126
Author(s):  
Tetsuro Hemmi ◽  
Koji Nakayama ◽  
Katsunori Asano ◽  
Tetsuya Miyazawa ◽  
Hidekazu Tsuchida
Keyword(s):  
Stress Test ◽  
Process Condition ◽  
Device Fabrication ◽  
Pin Diode ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Half Loop ◽  
Additional Process ◽  
Voltage Degradation ◽  
A Current

ABSTRACTThe forward voltage degradation in 4H-SiC PiN diodes with a simplified process and that in 4H-SiC pin diodes with additional processes are investigated. Photoluminescence images were also observed to identify the cause of forward voltage degradation. The forward voltage degradations of 4H-SiC PiN diodes with additional processes were larger than those with a simplified process. Observing photoluminescence images of diodes after a current stress test showed that less than 25% of Shockley-type stacking faults in 4H-SiC PiN diodes with a simplified process are caused by half-loop dislocations, which are generated not only in the additional processes but also in the whole device fabrication process. With additional processes, those rates are over 65%, which may be reduced by eliminating half-loop dislocations due to the optimization of the process condition and sequence.

scholarly journals 10 kV Silicon Carbide PiN Diodes—From Design to Packaged Component Characterization

Energies ◽  
2019 ◽  
Vol 12 (23) ◽  
pp. 4566 ◽  
Author(s):  
Asllani ◽  
Morel ◽  
Phung ◽  
Planson
Keyword(s):  
Silicon Carbide ◽  
Leakage Current ◽  
Voltage Drop ◽  
Forward Bias ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Pulse Switching ◽  
Turn On ◽  
Forward Voltage Drop ◽  
Fabrication And Characterization

This paper presents the design, fabrication and characterization results obtained on the last generation (third run) of SiC 10 kV PiN diodes from SuperGrid Institute. In forward bias, the 59 mm2 diodes were tested up to 100 A. These devices withstand voltages up to 12 kV on wafer (before dicing, packaging) and show a low forward voltage drop at 80 A. The influence of the temperature from 25 °C to 125 °C has been assessed and shows that resistivity modulation occurs in the whole temperature range. Leakage current at 3 kV increases with temperature, while being three orders of magnitude lower than those of equivalent Si diodes. Double-pulse switching tests reveal the 10 kV SiC PiN diode’s outstanding performance. Turn-on dV/dt and di/dt are −32 V/ns and 311 A/µs, respectively, whereas turn-off dV/dt and di/dt are 474 V/ns and −4.2 A/ns.

Mechanisms of Stacking Fault Growth in SiC PiN Diodes

2004 ◽  
Vol 815 ◽  
Author(s):  
R. E. Stahlbush ◽  
M. E. Twigg ◽  
J. J. Sumakeris ◽  
K. G. Irvine ◽  
P. A. Losee
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Stacking Fault ◽  
Drift Region ◽  
Pin Diodes ◽  
Current Time ◽  
Partial Dislocations ◽  
Initial Evolution ◽  
A Chain ◽  
Fault Growth

AbstractThe early development of stacking faults in SiC PiN diodes fabricated on 8° off c-axis 4H wafers has been studied. The 150μm drift region and p-n junction were epitaxially grown. The initial evolution of the stacking faults was examined by low injection electroluminescence using current-time product steps as low as 0.05 coul/cm2. The properties of the dislocations present before electrical stressing were determined based on previously observed differences of Si-core and C-core partial dislocations and the patterns of stacking fault expansion. The initial stacking fault expansion often forms a chain of equilateral triangles and at higher currents and/or longer times these triangles coalesce. All of the faulting examined in this paper originated between 10 and 40 μm below the SiC surface. The expansion rate of the bounding partial dislocations is very sensitive to the partials' line directions, their core types and the density of kinks. From these patterns it is concluded that the stacking faults originate from edge-like basal plane dislocations that have Burgers vectors either parallel or anti-parallel to the off-cut direction. Evidence for dislocation conversions between basal-plane and threading throughout the epitaxial drift region is also presented.

Study of Forward Voltage Drift in Diffused SiC PiN Diodes Doped by Al or B

2005 ◽  
Vol 483-485 ◽  
pp. 989-992 ◽  
Author(s):  
S.I. Maximenko ◽  
Stanislav I. Soloviev ◽  
A.E. Grekov ◽  
A.V. Bolotnikov ◽  
Ying Gao ◽  
...  
Keyword(s):  
Current Density ◽  
Room Temperature ◽  
Stacking Faults ◽  
Applied Current ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Applied Current Density ◽  
Voltage Drift ◽  
Significant Change ◽  
Degradation Testing

The degradation of diffused SiC PIN diodes during forward-biased operation was studied by first fabricating PIN diodes by diffusion of aluminum or boron into 4H-SiC substrates with n-type 10-15 µm thick epilayers doped by nitrogen up to 5x1015cm-3. The formed diodes were subjected to degradation testing under an applied current density of 200A/cm2 at room temperature. The majority of the Al diffused diodes demonstrated a voltage drift, ΔVf, of more than 2 V, while B-doped diodes showed no significant change in forward voltage. The EBIC mode of SEM was employed to monitor nucleation and expansion of stacking faults.

Effects of Basal Plane Dislocation Density in 4H-SiC Substrate on Degradation of Body-Diode Forward Voltage

2016 ◽  
Vol 858 ◽  
pp. 384-388 ◽  
Author(s):  
Naoyuki Kawabata ◽  
Atsushi Tanaka ◽  
Masatoshi Tsujimura ◽  
Yoshinori Ueji ◽  
Kazuhiko Omote ◽  
...  
Keyword(s):  
Basal Plane ◽  
Field Effect Transistors ◽  
Forward Bias ◽  
Oxide Semiconductor ◽  
Strong Positive Correlation ◽  
Forward Voltage ◽  
Bias Stress ◽  
Before And After ◽  
Basal Plane Dislocation ◽  
The Difference

We investigated the effect of the basal plane dislocation (BPD) density in 4H-silicon carbide (SiC) substrates on the forward voltage (Vsd) degradation of body-diodes. Using reflection X-ray topography, the BPD density was automatically estimated from the substrates prior to fabrication of metal–oxide–semiconductor field-effect transistors (MOSFETs). A strong positive correlation was found between the Vsd shift, which was calculated from the difference before and after forward bias stress at 160 A/cm2 for ~500 hours, and the BPD density of the substrate. We show that it is possible to predict Vsd shifts from the BPD densities of SiC substrates prior to the fabrication of MOSFETs. In addition, we examined the origin of stacking faults (SFs) as a result of the application of forward bias stress. We presume that SFs are formed by BPDs converted to threading edge dislocations at the epi/sub interface, as well as by BPDs penetrating into the epitaxial layer.

Performance of Silicon Carbide PiN Diodes Fabricated on Basal Plane Dislocation-Free Epilayers

2006 ◽  
Vol 527-529 ◽  
pp. 371-374 ◽  
Author(s):  
Ze Hong Zhang ◽  
A.E. Grekov ◽  
Priyamvada Sadagopan ◽  
S.I. Maximenko ◽  
Tangali S. Sudarshan
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Surface Damage ◽  
Induced Current ◽  
Pin Diodes ◽  
Current Stressing ◽  
Forward Current ◽  
Nucleation Sites ◽  
Basal Plane Dislocation ◽  
Electron Beam Induced Current

The nucleation sites of stacking faults (SFs) during forward current stress operation of 4H-SiC PiN diodes were investigated by the electron beam induced current (EBIC) mode of scanning electron microscopy (SEM), and the primary SF nucleation sites were found to be basal plane dislocations (BPDs). Damage created on the diode surface also acts as SF nucleation sites. By using a novel BPD-free SiC epilayer, and avoiding surface damage, PiN diodes were fabricated which did not exhibit SF formation under current stressing at 200A/cm2 for 3 hours.

Degradation of Majority Carrier Conductions and Blocking Capabilities in 4H-SiC High Voltage Devices due to Basal Plane Dislocations

2008 ◽  
Vol 1069 ◽  
Author(s):  
Sei-Hyung Ryu ◽  
Qingchun Zhang ◽  
Husna Fatima ◽  
Sarah Haney ◽  
Robert Stahlbush ◽  
...  
Keyword(s):  
High Voltage ◽  
Basal Plane ◽  
Voltage Drop ◽  
Schottky Diodes ◽  
Forward Bias ◽  
Stacking Faults ◽  
Majority Carrier ◽  
Before And After ◽  
Forward Voltage Drop ◽  
Basal Plane Dislocation

ABSTRACTThis paper presents the effect of recombination-induced stacking faults on the drift based forward conduction and leakage currents of high voltage 4H-SiC power devices. To show the effects, 10 kV 4H-SiC MPS (Merged PiN Schottky) diodes have been fabricated on a standard wafer and a low BPD (Basal Plane Dislocation) wafer, and their IV characteristics were evaluated before and after a forward bias stress, which resulted in minority carrier recombination and conductivity modulation in the drift epilayer of the diodes. After the stressing, the diode fabricated on standard wafer showed a significant increase in forward voltage drop, as well as a marked increase in leakage current, which were due to induction of stacking faults. The diode on the low BPD wafer showed very little change after the stress because the induction of stacking faults was minimized. Similar results were also observed on a 10 kV 4H-SiC DMOSFET. The results suggest that recombination-induced stacking faults are detrimental to all device types, and injection of minority carriers in majority carrier devices should be avoided at all times.

VF Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers

2014 ◽  
Vol 778-780 ◽  
pp. 851-854 ◽  
Author(s):  
Chiharu Ota ◽  
Johji Nishio ◽  
Kazuto Takao ◽  
Takashi Shinohe
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Optical Observation ◽  
Etch Pits ◽  
Pin Diodes ◽  
Bipolar Devices ◽  
Basal Plane Dislocation ◽  
Pl Mapping ◽  
Koh Etching ◽  
Free Area

In this paper, we found origin of VFdegradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A VFdegradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered VFdegradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.

Comparative Evaluation of Forward Voltage Degradation due to Propagating and Converted Basal Plane Dislocations

2018 ◽  
Vol 924 ◽  
pp. 143-146 ◽  
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Strong Correlation ◽  
Basal Plane ◽  
Comparative Evaluation ◽  
Epitaxial Layers ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Forward Current ◽  
Voltage Degradation ◽  
The Relationship ◽  
Drift Layer

This study investigated the relationship between the forward voltage degradation induced by SSF expansion and (a) BPD density in substrates and epitaxial layers of SiC, and (b) the temperature during the application forward current to the pin diodes. The Vf shift caused by the BPDs in the drift layer simply depended on the BPD density. However, no correlation was initially observed between the Vf shift and BPD density in the substrate; instead a strong correlation was observed between the Vf shift and the device temperature measured when applying the current stress. Thus when we selected samples which show the same temperature at that time, a correlation was observed between the Vf shift and the BPD density in the SiC substrate, with the slope corresponding to the former, drift layer relationship. Therefore, due to the high BPD density in the SiC substrate, suppressing the Vf shift due to BPD density in this region is highly important, and a combination of approaches is therefore proposed in order to reduce the overall forward voltage degradation.

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