Enhanced Breakdown Voltage of Si-GaN Monolithic Heterogeneous Integrated Cascode FETs by the Device Structure Design

In this work, the factors affecting the breakdown voltage of Si-GaN monolithic heterogeneous integrated Casccode FET fabricated by transfer printing were investigated. These two factors are the avalanche breakdown resistance of the Si device and the thickness of SiN electrical isolation layer. Two kinds of device structures, Si MOSFET and Si laterally-diffused MOSFET (LDMOSFET), were designed to study the effect of the avalanche breakdown resistance of the Si devices on the breakdown characteristics of Cascode FET. The effect of the thickness of SiN electrical isolation layer was analyzed. Finally, the breakdown voltage of monolithic integrated Cascode FET reached 770 V.

Investigation of the effect of doping the GaN buffer layer with carbon on the avalanche breakdown effect of normally open HEMT AlGaN/AlN/GaN transistors

The influence of the GaN buffer layer doped with carbon on the avalanche breakdown effect of normally open HEMT AlGaN / AlN / GaN transistors was studied. The avalanche breakdown was simulated in a structure where the gate length is LG = 0.3 mkm, the distance between the source and gate is LSG = 1.5 mkm, and the distance between the gate and drain is LGD = 2.2 mkm. For modeling, consider a layer doped with carbon, the thickness of which is 0.3 mkm, and the layer is located at a distance of 20 nm from the channel. The Simulation showed that with an increase in the concentration of carbon doping of the buffer, the breakdown voltage increases in the range UB = 225 – 360 (V). When the layer thickness changes to 0.4 mkm, the breakdown voltage increases in the range UB = 230 – 446 (V). For a structure where the gate length is LG = 0.8 mkm, the distance between the source and the gate is LSG = 1.0 mkm, the distance between the gate and drain is LGD = 3.0 mkm, the breakdown voltage increases in the range UB = 300 – 622 (V).

Switching overvoltages protection of power electronics converters with gate turn-off thyristors

Using the developed models in the “Simulink” visual programming environment of the “Matlab” application package using the “SimPowerSystem” and “Simscape Electrical” libraries, a comparative analysis of methods and techniques for limiting switching overvoltages in power converters, which are controlled by unlocking two-operation thyristors, was performed. The choice of a specific means of limitation is individual for each converter and depends on many factors - the power of the converter, the current-voltage characteristics of thyristors, the parameters of the power supply, and so on. Studies have shown that the most effective protection against voltage pulses with short duration and significant amplitude is the use of “Transient Voltage Suppressors” limiting diodes, the action of which is based on the use of avalanche breakdown during the time of thyristor unlocking.

Грибовидная меза-структура для лавинных фотодиодов на гетероструктурах InAlAs/InGaAs

Mushroom mesa structure for InAlAs/InGaAs avalanche photodiodes (APD) was proposed and investigated. APD heterostructrures were grown by molecular-beam epitaxy. Fabricated APDs with sensitive area diameter of about 30 micron were passivated by SiN deposition and demonstrate avalanche breakdown voltage Vbr ~ 70-80 V. At applied bias of 0.9 Vbr the dark current was ~ 75-200 nA. The single-mode coupled APDs demonstrate responsivity at a gain of unity is high than 0.5A/W at 1550 nm.