Structural study of single Shockley stacking faults terminated near substrate/epilayer interface in 4H-SiC

Structural analysis is carried out of a single Shockley stacking fault (1SSF) that terminates near the substrate/epilayer interface and originally expanded from a basal plane dislocation segment near the epilayer surface of 4H-SiC. The characteristic zigzag structure is found for the partial dislocations (PDs), with microscopic connecting angles of almost 120°. It has been suggested that the microscopic construction of PDs might be limited by the Peierls valley. The termination line near the substrate/epilayer interface was found to have 30° Si-core and 90° Si-core PDs. This combination is the same as that found near the surface of the epilayer in commonly observed 1SSFs. Penetrating BPDs of this kind were also found experimentally for the first time. For the currently proposed charts for the 1SSF expansions, photoluminescence imaging during UV illumination is one of the nondestructive analysis methods that can provide the structural information and expected expansion shapes of the 1SSFs.

Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

Progress in Bulk 4H SiC Crystal Growth for 150 mm Wafer Production

The thermoelastic stress, mechanical properties and defect content of bulk 4H n-type SiC crystals were investigated following adjustments to the PVT growth cell configuration that led to a 40% increase in growth rate. The resulting 150 mm wafers were compared with wafers produced from a control process in terms of wafer bow and warp, and dislocation density. Wafer shape was found to be comparable among the processes, indicating minimal impact on internal stress. Threading edge and threading screw dislocation densities increased and decreased, respectively, while basal plane dislocation densities were unaffected by the increase in growth rate. Loss of wafer planar stability was observed in certain cases. The elastic modulus was measured to be in the range of approximately 420-450 GPa for selected stable and unstable wafers, and was found to correspond to resistivity.

Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC

Basal plane dislocations (BPDs) in 4H silicon carbide (SiC) crystals grown using the physical vapor transport (PVT) method are diminishing the performance of SiC-based power electronic devices such as pn-junction diodes or MOSFETs. Therefore, understanding the generation and movement of BPDs is crucial to grow SiC suitable for device manufacturing. In this paper, the impact of the cooldown step in PVT-growth on the defect distribution is investigated utilizing two similar SiC seeds and identical growth parameters except for a cooldown duration of 40 h and 70 h, respectively. The two resulting crystals were cut into wafers, which were characterized by birefringence imaging and KOH etching. The initial defect distribution of the seed wafer was characterized by synchrotron white beam X-ray topography (SWXRT) mapping. It was found that the BPD density increases with a prolonged cooldown time. Furthermore, small angle grain boundaries based on threading edge dislocation (TED) arrays, which are normally only inherited by the seed, were also generated in the case of the crystal cooled down in 70 h. The role of temperature gradients inside the crystal during growth and post-growth concerning the generation of shear stress is discussed and supported by numerical calculations.

Study on Dislocation Behaviors during PVT Growth of 4H-SiC

The generation and transformation of dislocations in 4H-SiC crystals grown by PVT were investigated. Experiments were carried out in two stages for more comprehensive observation on dislocation behaviors. For the first stage known as initial growth, we investigated mainly the seed and grown interface. The behavior and transition of the dislocations in grown crystal were observed along the length of the crystal at second stage. The formation of threading edge dislocations (TEDs) strongly depends on the surface morphologies related with internal temperature gradients during crystal growth. The basal plane dislocation (BPDs) and threading screw dislocation (TSDs) cause from the seed crystal and formed at the initial stage of growth were gradually decreased in number along the length of the crystal and under certain conditions such as distorted stresses, dislocations were converted into other types of dislocations.

New SiC Epitaxial Growth Process with up to 100% BPD to TED Defect Conversion on 150mm Hot-Wall CVD Reactor

The future challenges for SiC device technology are cost reduction and increased reliability. A key point to achieve that is the increase of yield during epitaxial layer growth through the reduction of structural defects (such as basal plane dislocations and triangle defects), an increased thickness and doping uniformity, and a high growth rate. Despite significant advancements in SiC epitaxial growth technology, it still constitutes a big challenge to find the optimum working point at which all those requirements are fulfilled. By implementing a new epitaxial layer growth process, we are able to grow basal plane dislocation free epitaxial layers, while the density of other structural defects remains low. Additionally, intra-wafer thickness and doping uniformities of the epitaxial layers are further improved.