32nm Node Highly Reliable Cu/Low-k Integration Technology with CuMn Alloy Seed

MRS Proceedings ◽

10.1557/opl.2011.1261 ◽

2011 ◽

Vol 1335 ◽

Author(s):

Shaoning Yao ◽

Vincent McGahay ◽

Matthew S. Angyal ◽

Andrew H. Simon ◽

Tom C. Lee ◽

...

Keyword(s):

Process Integration ◽

Integration Technology ◽

Cu Interconnect ◽

Interconnect Technology ◽

Low K

ABSTRACTThis paper introduces a highly reliable Cu interconnect technology at the 32 nm node with CuMn alloy seed. A CuMn alloy liner seed process combined with a non-gouging liner has been integrated into the minimum-pitch wiring level. Stress migration fails with CuMn seed at plate-below-via structures were shut down by a non-gouging liner process. Integration with gouging liner and non-gouging liner is compared, and results of interaction with CuMn seed are discussed in this paper.

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A scalable low-k/Cu interconnect technology using i self-assembled ultra-low-k porous silica films

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. ◽

10.1109/icsict.2004.1435055 ◽

2005 ◽

Author(s):

T. Kikkawa ◽

Y. Oku ◽

K. Kohmura ◽

N. Fujii ◽

H. Tanaka ◽

...

Keyword(s):

Porous Silica ◽

Silica Films ◽

Self Assembled ◽

Cu Interconnect ◽

Interconnect Technology ◽

Low K

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A 65nm-node, Cu interconnect technology using porous SiOCH film (k=2.5) covered with ultra-thin, low-k pore seal (k=2.7)

IEEE International Electron Devices Meeting 2003 ◽

10.1109/iedm.2003.1269411 ◽

2004 ◽

Cited By ~ 2

Author(s):

M. Tada ◽

Y. Harada ◽

T. Tamura ◽

N. Inoue ◽

F. Ito ◽

...

Keyword(s):

Cu Interconnect ◽

Interconnect Technology ◽

Low K

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BEOL process integration technology for 45 nm node porous low-k/copper interconnects

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. ◽

10.1109/iitc.2005.1499903 ◽

2005 ◽

Cited By ~ 2

Author(s):

N. Matsunaga ◽

N. Nakamura ◽

K. Higashi ◽

H. Yamaguchi ◽

T. Watanabe ◽

...

Keyword(s):

Process Integration ◽

Copper Interconnects ◽

Integration Technology ◽

Low K

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Robust process integration of 0.78 μm/sup 2/ embedded SRAM with NiSi gate and low-K Cu interconnect for 90 nm SoC applications

2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407) ◽

10.1109/vlsit.2003.1221090 ◽

2004 ◽

Author(s):

Y.W. Kim ◽

J.H. Ahn ◽

T.S. Park ◽

C.B. Oh ◽

K.T. Lee ◽

...

Keyword(s):

Process Integration ◽

Cu Interconnect ◽

Robust Process ◽

Low K ◽

Embedded Sram

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90 nm generation, 300 mm wafer low k ILD/Cu interconnect technology

Proceedings of the IEEE 2003 International Interconnect Technology Conference (Cat. No.03TH8695) ◽

10.1109/iitc.2003.1219699 ◽

2004 ◽

Cited By ~ 5

Author(s):

C.-H. Jan ◽

J. Bielefeld ◽

M. Buehler ◽

V. Chikamane ◽

K. Fischer ◽

...

Keyword(s):

Cu Interconnect ◽

Interconnect Technology ◽

Low K

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300 mm process integration for 0.13 μm generation with Cu/low-k interconnect technology

International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) ◽

10.1109/iedm.2001.979577 ◽

2002 ◽

Author(s):

W. Chang ◽

C.C. Chen ◽

J.C. Lu ◽

S.J. Liou ◽

W.J. Tsai ◽

...

Keyword(s):

Process Integration ◽

Interconnect Technology ◽

Low K

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Feasibility Study of Process Integration for High Aspect Ratio Hard-Mask Scheme Technologies of Low-k/Cu Interconnect Fabrication

Materials and Manufacturing Processes ◽

10.1080/10426914.2010.529592 ◽

2011 ◽

Vol 26 (9) ◽

pp. 1104-1110 ◽

Cited By ~ 2

Author(s):

Chun-Jen Weng

Keyword(s):

Aspect Ratio ◽

Feasibility Study ◽

High Aspect Ratio ◽

Process Integration ◽

Hard Mask ◽

Cu Interconnect ◽

Low K

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Preparation of Nano Structured SiOC Thin Film for Low k Application

Journal of Nano Research ◽

10.4028/www.scientific.net/jnanor.11.85 ◽

2010 ◽

Vol 11 ◽

pp. 85-88 ◽

Cited By ~ 4

Author(s):

Woo Teck Kwon ◽

J.H. Lee ◽

Soo Ryong Kim ◽

H.T. Kim ◽

Hyung Sun Kim ◽

...

Keyword(s):

Thin Film ◽

Dielectric Constant ◽

Dielectric Properties ◽

Dip Coating ◽

Interlayer Dielectrics ◽

Promising Application ◽

Cu Interconnect ◽

Interconnect Technology ◽

Low K ◽

Mim Capacitors

In our study, the dielectric properties of SiOC low k thin film derived from polyphenylcarbosilane were investigated as a potential interlayer dielectrics for Cu interconnect technology. A SiOC low k thin film was fabricated onto a n-type silicon wafer by dip coating using 30wt % polyphenylcarbosilane in cyclohexane. Curing of the film was performed in air at 300°C for 2h. The thickness of the film ranges from 1 μm to 1.7 μm. The dielectric constant was determined from the capacitance data obtained from metal/polyphenylcarbosilane/conductive Si MIM capacitors and shows a dielectric constant as low as 3.26 without porosity added. The SiOC low k thin film derived from polyphenylcarbosilane shows promising application as an interlayer dielectrics for Cu interconnect technology.

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