Resistive Losses at c-Si/a-Si:H/ZnO Contacts for Heterojunction Solar Cells

2007 ◽  
Vol 989 ◽  
Author(s):  
Florian Einsele ◽  
Phillip Johannes Rostan ◽  
Uwe Rau
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Fill Factor ◽  
High Efficiency ◽  
Surface Recombination ◽  
Open Circuit ◽  
Surface Recombination Velocity ◽  
High Hydrogen ◽  
Solar Cell Performance ◽  
Heterojunction Solar Cells

AbstractWe study resistive losses at (p)c-Si/(p)Si:H/(n)ZnO heterojunction back contacts for high efficiency silicon solar cells. We find that a low tunnelling resistance for the (p)a-Si:H/(n)ZnO part of the junction requires deposition of Si:H with a high hydrogen dilution RH > 40 resulting in a highly doped μc-Si:H layer. Such a μc-Si:H layer if deposited directly on a Si wafer yields a surface recombination velocity of S  180 cm/s. Using the same layer as part of a (p)c-Si/(p)Si:H/(n)ZnO back contact in a solar cell results in an open circuit voltage Voc = 640 mV and a fill factor FF = 80 %. Insertion of an (i)a-Si-layer between the μc-Si:H and the wafer leads to a further decrease of S and, for the solar cells to an increase of VOC. However, if the thickness of this intrinsic layer exceeds a threshold of 3 nm, resistive losses lead to a degradation of the fill factor of the solar cells. These resistive losses result from a valence band offset δEV between a-Si:H and c-Si of about 600 meV. The fill factor losses overcompensate the VOC gain such that there is no benefit of the (i)a-Si:H interlayer for the overall solar cell performance when using an (i)a-Si:H/(p)uc-Si:H double layer.

scholarly journals Numerical Simulation Analysis of Ag Crystallite Effects on Interface of Front Metal and Silicon in the PERC Solar Cell

Energies ◽  
2021 ◽  
Vol 14 (3) ◽  
pp. 592
Author(s):  
Myeong Sang Jeong ◽  
Yonghwan Lee ◽  
Ka-Hyun Kim ◽  
Sungjin Choi ◽  
Min Gu Kang ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
High Efficiency ◽  
Open Circuit Voltage ◽  
Surface Recombination ◽  
Open Circuit ◽  
Surface Recombination Velocity ◽  
Metal Interface ◽  
Ag Crystallites ◽  
Recombination Velocity

In the fabrication of crystalline silicon solar cells, the contact properties between the front metal electrode and silicon are one of the most important parameters for achieving high-efficiency, as it is an integral element in the formation of solar cell electrodes. This entails an increase in the surface recombination velocity and a drop in the open-circuit voltage of the solar cell; hence, controlling the recombination velocity at the metal-silicon interface becomes a critical factor in the process. In this study, the distribution of Ag crystallites formed on the silicon-metal interface, the surface recombination velocity in the silicon-metal interface and the resulting changes in the performance of the Passivated Emitter and Rear Contact (PERC) solar cells were analyzed by controlling the firing temperature. The Ag crystallite distribution gradually increased corresponding to a firing temperature increase from 850 ∘C to 950 ∘C. The surface recombination velocity at the silicon-metal interface increased from 353 to 599 cm/s and the open-circuit voltage of the PERC solar cell decreased from 659.7 to 647 mV. Technology Computer-Aided Design (TCAD) simulation was used for detailed analysis on the effect of the surface recombination velocity at the silicon-metal interface on the PERC solar cell performance. Simulations showed that the increase in the distribution of Ag crystallites and surface recombination velocity at the silicon-metal interface played an important role in the decrease of open-circuit voltage of the PERC solar cell at temperatures of 850–900 ∘C, whereas the damage caused by the emitter over fire was determined as the main cause of the voltage drop at 950 ∘C. These results are expected to serve as a steppingstone for further research on improvement in the silicon-metal interface properties of silicon-based solar cells and investigation on high-efficiency solar cells.

17.8%-efficient Amorphous Silicon Heterojunction Solar Cells on p-type Silicon Wafers

2006 ◽  
Vol 910 ◽  
Author(s):  
Qi Wang ◽  
Matt P. Page ◽  
Eugene Iwancizko ◽  
Yueqin Xu ◽  
Yanfa Yan ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Amorphous Silicon ◽  
High Efficiency ◽  
Short Circuit ◽  
Open Circuit ◽  
Layer Growth ◽  
Surface Recombination Velocity ◽  
Back Contact ◽  
P Type

AbstractWe have achieved an independently-confirmed 17.8% conversion efficiency in a 1-cm2, p-type, float-zone silicon (FZ-Si) based heterojunction solar cell. Both the front emitter and back contact are hydrogenated amorphous silicon (a-Si:H) deposited by hot-wire chemical vapor deposition (HWCVD). This is the highest reported efficiency for a HWCVD silicon heterojunction (SHJ) solar cell. Two main improvements lead to our most recent increases in efficiency: 1) the use of textured Si wafers, and 2) the application of a-Si:H heterojunctions on both sides of the cell. Despite the use of textured c-Si to increase the short-circuit current, we were able to maintain the same 0.65 V open-circuit voltage as on flat c-Si. This is achieved by coating a-Si:H conformally on the c-Si surfaces, including covering the tips of the anisotropically-etched pyramids. A brief atomic H treatment before emitter deposition is not necessary on the textured wafers, though it was helpful in the flat wafers. It is essential to high efficiency SHJ solar cells that the emitter grows abruptly as amorphous silicon, instead of as microcrystalline or epitaxial Si. The contact on each side of the cell comprises a thin (< 5 nm) low substrate temperature (~100°C) intrinsic a-Si:H layer, followed by a doped layer. Our intrinsic layers are deposited at 0.3-1.2 nm/s. The doped emitter and back-contact layers were deposited at a higher temperature (>200°C) and grown from PH3/SiH4/H2 and B2H6/SiH4/H2 doping gas mixtures, respectively. This combination of low (intrinsic) and high (doped layer) growth temperatures was optimized by lifetime and surface recombination velocity measurements. Our rapid efficiency advance suggests that HWCVD may have advantages over plasma-enhanced (PE) CVD in fabrication of high-efficiency heterojunction c-Si cells; there is no need for process optimization to avoid plasma damage to the delicate, high-quality, Si wafers.

Simulation of InAIN/Si Single-Heterojunction Solar Cells Using wxAMPS

2014 ◽  
Vol 665 ◽  
pp. 111-114 ◽  
Author(s):  
Ying Huang ◽  
Xiao Ming Shen ◽  
Xiao Feng Wei
Keyword(s):  
Solar Cells ◽  
Fill Factor ◽  
High Efficiency ◽  
Open Circuit Voltage ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Indium Content ◽  
Open Circuit ◽  
Heterojunction Solar Cells ◽  
Si Solar Cells

In this paper, InAlN/Si single-heterojunction solar cells have been theoretically simulated based on wxAMPS software. The photovoltaic parameters, such as open circuit voltage, short circuit current, fill factor and conversion efficiency were investigated with changing the indium content and thickness of n-InAlN layer. Simulation results show that the optimum efficiency of InAlN/Si solar cells is 23.1% under AM 1.5G spectral illuminations, with the indium content and thickness of n-InAlN layer are 0.65 and 600nm, respectively. The simulation would contribute to design and fabricate high efficiency InAlN/Si solar cells in experiment.

High-Efficiency HIT Solar Cells for Excellent Power Generating Properties

2008 ◽  
Vol 1123 ◽  
Author(s):  
Toshihiro Kinoshita ◽  
Daisuke Ide ◽  
Yasufumi Tsunomura ◽  
Shigeharu Taira ◽  
Toshiaki Baba ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Conversion Efficiency ◽  
Production Cost ◽  
High Efficiency ◽  
Open Circuit Voltage ◽  
Short Circuit ◽  
Open Circuit ◽  
Surface Recombination Velocity ◽  
Dominant Factor

AbstractIn order to achieve the widespread use of HIT (Hetero-junction with I etero-Intrinsic T ntrinsic Thin-layer) solar cells, it is important to reduce the power generating cost. There are three main approaches for reducing this cost: raising the conversion efficiency of the HIT cell, using a thinner wafer to reduce the wafer cost, and raising the open circuit voltage to obtain a better temperature coefficient. With the first approach, we have achieved the highest conversion efficiency values of 22.3%, confirmed by AIST, in a HIT solar cell. This cell has an open circuit voltage of 0.725 V, a short circuit current density of 38.9 mA/cm2 and a fill factor of 0.791, with a cell size of 100.5 cm2. The second approach is to use thinner Si wafers. The shortage of Si feedstock and the strong requirement of a lower sales price make it necessary for solar cell manufacturers to reduce their production cost. The wafer cost is an especially dominant factor in the production cost. In order to provide low-priced, high-quality solar cells, we are trying to use thinner wafers. We obtained a conversion efficiency of 21.4% (measured by Sanyo) for a HIT solar cell with a thickness of 85μm. Even better, there was absolutely no sagging in our HIT solar cell because of its symmetrical structure. The third approach is to raise the open circuit voltage. We obtained a remarkably higher Voc of 0.739 V with the thinner cell mentioned above because of its low surface recombination velocity. The high Voc results in good temperature properties, which allow it to generate a large amount of electricity at high temperatures.

scholarly journals Nanostructured Dielectric Layer for Ultrathin Crystalline Silicon Solar Cells

2017 ◽  
Vol 2017 ◽  
pp. 1-6
Author(s):  
Yusi Chen ◽  
Yangsen Kang ◽  
Jieyang Jia ◽  
Yijie Huo ◽  
Muyu Xue ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Reflection Loss ◽  
Dielectric Layer ◽  
Short Circuit ◽  
Surface Recombination ◽  
Dielectric Materials ◽  
Surface Recombination Velocity ◽  
Optical Simulation ◽  
Solar Cell Performance

Nanostructures have been widely used in solar cells due to their extraordinary photon management properties. However, due to poor pn junction quality and high surface recombination velocity, typical nanostructured solar cells are not efficient compared with the traditional commercial solar cells. Here, we demonstrate a new approach to design, simulate, and fabricate whole-wafer nanostructures on dielectric layer on thin c-Si for solar cell light trapping. The optical simulation results show that the periodic nanostructure arrays on dielectric materials could suppress the reflection loss over a wide spectral range. In addition, by applying the nanostructured dielectric layer on 40 μm thin c-Si, the reflection loss is suppressed to below 5% over a wide spectra and angular range. Moreover, a c-Si solar cell with 2.9 μm ultrathin absorber layer demonstrates 32% improvement in short circuit current and 44% relative improvement in energy conversion efficiency. Our results suggest that nanostructured dielectric layer has the potential to significantly improve solar cell performance and avoid typical problems of defects and surface recombination for nanostructured solar cells, thus providing a new pathway towards realizing high-efficiency and low-cost c-Si solar cells.

Dramatically promoted crystallization control of organolead triiodide perovskite film by a homogeneous cap for high efficiency planar-heterojunction solar cells

2016 ◽  
Vol 4 (32) ◽  
pp. 12535-12542 ◽  
Author(s):  
Weidong Zhu ◽  
Chunxiong Bao ◽  
Bihu Lv ◽  
Faming Li ◽  
Yong Yi ◽  
...  
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
High Efficiency ◽  
Cell Performance ◽  
High Quality ◽  
Solar Cell Performance ◽  
Heterojunction Solar Cells ◽  
Planar Heterojunction Solar Cells ◽  
Planar Heterojunction

A homogeneous cap-mediated crystallization strategy can be used to realize high-quality organolead triiodide perovskite (OTP) films with greatly enhanced solar cell performance.

scholarly journals Influence of Defect States and Thickness of Interface Layer On High Efficiency of c-Si/a-Si:H Heterojunction Solar Cells With Higher Bandgap a-Si:H(p) Layer By Simulation

2021 ◽  
Author(s):  
Venkanna Kanneboina
Keyword(s):  
Solar Cells ◽  
High Efficiency ◽  
Defect Density ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Interface Layer ◽  
Open Circuit ◽  
Defect States ◽  
Solar Cell Performance ◽  
Heterojunction Solar Cells

Abstract This paper presents the influence of defect states and thickness of interface layer on high efficiency of c-Si/a-Si:H heterojunction solar cells with higher bandgap emitter a-Si:H(p) layer by AFORSHET simulation tool. At first, the performance of Ag/ZnO/a-Si:H(p)/ a-Si:H(i)/ c-Si(n)/ a-Si:H(i)/ a-Si:H(n)/Ag heterojunction solar cells was studied by altering the thickness of a-Si:H(p) and a-Si:H(i) layers. The best values of open circuit voltage (Voc) (764.8 mV), short circuit current density (Jsc) (43.15 mA/cm2), fill factor (FF) (85.71) and efficiency(ɳ) (28.28%) were obtained at 3 nm of a-Si:H(p) and a-Si:H(i) layer. In the same structure, c-Si(n) interface was introduced in between c-Si(n) and a-Si:H(i) layer. It is found that the solar cell performance was not changed by varying defect density from 109-1014 cm-3 for thin (5 and 10 nm) interface layer and estimated values are 761.7 mV, 38.83 mA/cm2, 86.09%, 25.46% correspond to Voc, Jsc, FF, ɳ respectively. For very thick interface layer, defect density has shown huge impact on the device performance. At 1 µm, the Voc, FF and ɳ values have been changed from 760.2 to 653.2 mV, 85.9 to 80.76% and 22.94 to 18.47% for the defect density of 109 to 1014 cm-3 respectively.

scholarly journals Solution-processed TiO2 as a hole blocking layer in PEDOT:PSS/n-Si heterojunction solar cells

2020 ◽  
Vol 11 ◽  
pp. 7
Author(s):  
Md. Enamul Karim ◽  
A.T.M. Saiful Islam ◽  
Yuki Nasuno ◽  
Abdul Kuddus ◽  
Ryo Ishikawa ◽  
...  
Keyword(s):  
Solar Cells ◽  
Collection Efficiency ◽  
Photovoltaic Performance ◽  
Surface Recombination ◽  
Open Circuit ◽  
Surface Recombination Velocity ◽  
Blocking Layer ◽  
Solution Processed ◽  
Heterojunction Solar Cells ◽  
Hole Blocking Layer

The junction properties at the solution-processed titanium dioxide (TiO2)/n-type crystalline Si(n-Si) interface were studied for poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS)/n-Si heterojunction solar cells by the steady-state photovoltaic performance and transient reverse recovery characterizations. The power conversion efficiency could be increased from 11.23% to 13.08% by adjusting the layer thickness of TiO2 together with increasing open-circuit voltage and suppressed dark saturation current density. These findings originate from the enhancement of the carrier collection efficiency at the n-Si/cathode interface. The transient reverse recovery characterization revealed that the surface recombination velocity S was ∼375 cm/s for double TiO2 interlayer of ∼2 nm thickness. This value was almost the same as that determined by microwave photoconductance decay measurement. These findings suggest that solution-processed TiO2 has potential as a hole blocking layer for the crystalline Si photovoltaics.

scholarly journals Fabrication of Affordable and Sustainable Solar Cells Using NiO/TiO2 P-N Heterojunction

2018 ◽  
Vol 2018 ◽  
pp. 1-7 ◽  
Author(s):  
Kingsley O. Ukoba ◽  
Freddie L. Inambao ◽  
Andrew C. Eloka-Eboka
Keyword(s):  
Solar Cells ◽  
Solar Cell ◽  
Fill Factor ◽  
Open Circuit Voltage ◽  
Spray Pyrolysis Technique ◽  
Low Cost ◽  
Short Circuit ◽  
Short Circuit Current ◽  
Open Circuit ◽  
Heterojunction Solar Cells

The need for affordable, clean, efficient, and sustainable solar cells informed this study. Metal oxide TiO2/NiO heterojunction solar cells were fabricated using the spray pyrolysis technique. The optoelectronic properties of the heterojunction were determined. The fabricated solar cells exhibit a short-circuit current of 16.8 mA, open-circuit voltage of 350 mV, fill factor of 0.39, and conversion efficiency of 2.30% under 100 mW/cm2 illumination. This study will help advance the course for the development of low-cost, environmentally friendly, and sustainable solar cell materials from metal oxides.

Effects of Band Offsets on a-Sic:H/c-Si Heterojunction Solar Cell Performance

1998 ◽  
Vol 507 ◽  
Author(s):  
M. W. M. Van Cleef ◽  
F. A. Rubinelli ◽  
R. E. I. Schropp
Keyword(s):  
Solar Cells ◽  
Valence Band ◽  
Conduction Band ◽  
Fill Factor ◽  
Open Circuit ◽  
Tunnel Barrier ◽  
Solar Cell Performance ◽  
Band Offsets ◽  
Heterojunction Solar Cells ◽  
Simulation Results

ABSTRACTWe used the internal photoemission technique to determine the exact valence and conduction band offsets at the a-SiC:H/c-Si interface and investigated with numerical simulations their effects on the photocarrier collection in p+a-SiC:H/n c-Si heterojunction solar cells. The valence and conduction band offsets were found to be 0.60 eV and 0.55 eV, respectively. Simulation results show that a high valence band offset increases the open circuit voltage (higher built-in potential) but on the other hand can decrease the fill factor (by blocking the collection of photogenerated holes at the front contact). Interestingly, despite having a large barrier inside the valence band (ΔEv = 0.6 eV), our highly doped p+a-SiC:H/n c-Si heterojunction solar cells show no collection problems (FF= 0.73). Both IPE measurements and simulation results indicate that tunneling of holes through this barrier in the valence band can explain this effect. For thin highly doped (Eact = 0.33 eV) p+a-SiC:H layers, the tunnel barrier becomes very narrow (< 70 Å) and the tunneling probability is strongly enhanced.

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