Epitaxial Growth of High-κ Dielectrics for GaN MOSFETs

2008 ◽  
Vol 1068 ◽  
Author(s):  
Jesse S. Jur ◽  
Ginger D. Wheeler ◽  
Matthew T. Veety ◽  
Daniel J. Lichtenwalner ◽  
Douglas W. Barlage ◽  
...  
Keyword(s):  
Rare Earth ◽  
Epitaxial Growth ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Rare Earth Oxides ◽  
Oxide Semiconductor ◽  
Native Oxide ◽  
Enhancement Mode ◽  
Effect Transistor ◽  
The Rare Earth

ABSTRACTHigh-dielectric constant (high-κ) oxide growth on hexagonal-GaN (on sapphire) is examined for potential use in enhancement-mode metal oxide semiconductor field effect transistor (MOSFET). Enhancement-mode MOSFET devices (ns > 4×1013 cm−2) offer significant performance advantages, such as greater efficiency and scalability, as compared to heterojunction field effect transistor (HFET) devices for use in high power and high frequency GaN-based devices. High leakage current and current collapse at high drive conditions suggests that the use of a high-κ insulating layer is principle for enhancement-mode MOSFET development. In this work, rare earth oxides (Sc, La, etc.) are explored due to their ideal combination of permittivity and high band gap energy. However, a substantial lattice mismatch (9-21%) between the rare earth oxides and the GaN substrate results in mid-gap defect state densities and growth dislocations. The epitaxial growth of the rare earth oxides by molecular beam epitaxy (MBE) on native oxide passivated-GaN is examined in an effort to minimize these growth related defects and other growth-related limitations. Growth of the oxide on GaN is characterized analytically by RHEED, XRD, and XPS. Preliminary MOS electrical analysis of a 50 Å La2O3 on GaN shows superior leakage performance as compared to significantly thicker Si3N4 dielectric.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

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