Interfacial Solid-State Oxidation Reactions In The Sn-Doped In2O3 On Si And Si0.85Ge0.15 Alloy Systems

1994 ◽  
Vol 345 ◽  
Author(s):  
Cleva W. Ow-Yang ◽  
Yuzo Shigesato ◽  
Rita Mohanty ◽  
David C. Paine
Keyword(s):  
Solid State ◽  
Surface Morphology ◽  
Oxide Layer ◽  
Silicon Wafer ◽  
Thick Layer ◽  
Silicon Wafers ◽  
Oxidation Reactions ◽  
Planar Surface ◽  
Amorphous Oxide ◽  
P Type

AbstractWe have experimentally demonstrated that the interface between ITO and Si or Si0.85Ge0.15 is metastable, with silicon reducing ITO to form an amorphous oxide layer and In metal. A 400nm-thick ITO layer was deposited on two types of substrates: p-type, <100> silicon wafers and a silicon wafer with a 400nm-thick layer of Si0.85Ge0.15 grown by CVD. Annealing of the ITO/Si system resulted in the growth of a 5nm-thick planar, interfacial SiO2 layer and the formation of In metal in the ITO above the SiO2 layer. In contrast, annealing of the ITO/Si0.85Ge0.15 system produced an interfacial Si0.85Ge0.15O2 layer that was non-uniform in thickness and which had a non-planar surface morphology. As-deposited and annealed samples were characterized by HREM, EDS, and C-V measurements. Thermodynamic and kinetic arguments predicted both of the different reaction paths that were observed in the two systems.

The Study of Surface Morphology and Roughness of Silicon Wafers Treated by Plasma

2020 ◽  
Vol 980 ◽  
pp. 88-96
Author(s):  
Jin Rui Bai ◽  
Rui Xiang Hou
Keyword(s):  
Surface Morphology ◽  
Plasma Treatment ◽  
Silicon Wafer ◽  
Processing Time ◽  
Surface Region ◽  
Silicon Wafers ◽  
Plasma Process ◽  
Plasma Doping ◽  
Atom Force Microscope ◽  
The Way

Plasma is generally used for the doping of semiconductors. During plasma doping process, plasma interacts with the surface of semiconductor. As a result, defects are induced in the surface region. In this work, the surface morphology and roughness of silicon wafer caused by plasma treatment is studied by use of atom force microscope (AFM). It is found that, during the plasma process, each of the processing time of plasma, location of silicon wafer in plasma and the way of placement of silicon wafer has an influence on the surface morphology and roughness and the reason is discussed. The interaction between plasma and the surface of silicon wafer is qualitatively discussed.

Study of the electrical properties of  Cz p-type solar-grade silicon wafers against the high-temperature processes

2021 ◽  
Vol 127 (6) ◽  
Author(s):  
Mohamed Maoudj ◽  
Djoudi Bouhafs ◽  
Nacer Eddine Bourouba ◽  
Abdelhak Hamida-Ferhat ◽  
Abdelkader El Amrani
Keyword(s):  
High Temperature ◽  
Electrical Properties ◽  
Silicon Wafers ◽  
Solar Grade Silicon ◽  
High Temperature Processes ◽  
Grade Silicon ◽  
P Type

scholarly journals The Influence of Wire Speed on Phase Transitions and Residual Stress in Single Crystal Silicon Wafers Sawn by Resin Bonded Diamond Wire Saw

Micromachines ◽  
2021 ◽  
Vol 12 (4) ◽  
pp. 429
Author(s):  
Tengyun Liu ◽  
Peiqi Ge ◽  
Wenbo Bi
Keyword(s):  
Residual Stress ◽  
Surface Layer ◽  
Phase Transitions ◽  
Single Crystal ◽  
Amorphous Silicon ◽  
Silicon Wafer ◽  
Single Crystal Silicon ◽  
Silicon Wafers ◽  
Crystal Silicon ◽  
Diamond Wire

Lower warp is required for the single crystal silicon wafers sawn by a fixed diamond wire saw with the thinness of a silicon wafer. The residual stress in the surface layer of the silicon wafer is the primary reason for warp, which is generated by the phase transitions, elastic-plastic deformation, and non-uniform distribution of thermal energy during wire sawing. In this paper, an experiment of multi-wire sawing single crystal silicon is carried out, and the Raman spectra technique is used to detect the phase transitions and residual stress in the surface layer of the silicon wafers. Three different wire speeds are used to study the effect of wire speed on phase transition and residual stress of the silicon wafers. The experimental results indicate that amorphous silicon is generated during resin bonded diamond wire sawing, of which the Raman peaks are at 178.9 cm−1 and 468.5 cm−1. The ratio of the amorphous silicon surface area and the surface area of a single crystal silicon, and the depth of amorphous silicon layer increases with the increasing of wire speed. This indicates that more amorphous silicon is generated. There is both compressive stress and tensile stress on the surface layer of the silicon wafer. The residual tensile stress is between 0 and 200 MPa, and the compressive stress is between 0 and 300 MPa for the experimental results of this paper. Moreover, the residual stress increases with the increase of wire speed, indicating more amorphous silicon generated as well.

Experimental investigation into polishing of monocrystalline silicon wafer using double-disc chemical assisted magnetorheological finishing process

2021 ◽  
pp. 095440622098384
Author(s):  
Mayank Srivastava ◽  
Pulak M Pandey
Keyword(s):  
Surface Roughness ◽  
Silicon Wafer ◽  
Flow Rate ◽  
Silicon Wafers ◽  
Monocrystalline Silicon ◽  
Slurry Flow ◽  
Magnetorheological Finishing ◽  
Finishing Process ◽  
Process Factors ◽  
Slurry Flow Rate

In the present work, a novel hybrid finishing process that combines the two preferred methods in industries, namely, chemical-mechanical polishing (CMP) and magneto-rheological finishing (MRF), has been used to polish monocrystalline silicon wafers. The experiments were carried out on an indigenously developed double-disc chemical assisted magnetorheological finishing (DDCAMRF) experimental setup. The central composite design (CCD) was used to plan the experiments in order to estimate the effect of various process factors, namely polishing speed, slurry flow rate, percentage CIP concentration, and working gap on the surface roughness ([Formula: see text]) by DDCAMRF process. The analysis of variance was carried out to determine and analyze the contribution of significant factors affecting the surface roughness of polished silicon wafer. The statistical investigation revealed that percentage CIP concentration with a contribution of 30.6% has the maximum influence on the process performance followed by working gap (21.4%), slurry flow rate (14.4%), and polishing speed (1.65%). The surface roughness of polished silicon wafers was measured by the 3 D optical profilometer. Scanning electron microscopy (SEM) and atomic force microscopy (AFM) were carried out to understand the surface morphology of polished silicon wafer. It was found that the surface roughness of silicon wafer improved with the increase in polishing speed and slurry flow rate, whereas it was deteriorated with the increase in percentage CIP concentration and working gap.

scholarly journals Solid-State Redox Kinetics of CeO2 in Two-Step Solar CH4 Partial Oxidation and Thermochemical CO2 Conversion

Catalysts ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 723
Author(s):  
Mahesh Muraleedharan Nair ◽  
Stéphane Abanades
Keyword(s):  
Solid State ◽  
Solar Energy ◽  
Kinetic Models ◽  
Oxygen Carrier ◽  
Co2 Conversion ◽  
Oxidation Reactions ◽  
Redox Kinetics ◽  
Concentrated Solar Energy ◽  
Ceria Reduction ◽  
Kinetics Of

The CeO2/CeO2−δ redox system occupies a unique position as an oxygen carrier in chemical looping processes for producing solar fuels, using concentrated solar energy. The two-step thermochemical ceria-based cycle for the production of synthesis gas from methane and solar energy, followed by CO2 splitting, was considered in this work. This topic concerns one of the emerging and most promising processes for the recycling and valorization of anthropogenic greenhouse gas emissions. The development of redox-active catalysts with enhanced efficiency for solar thermochemical fuel production and CO2 conversion is a highly demanding and challenging topic. The determination of redox reaction kinetics is crucial for process design and optimization. In this study, the solid-state redox kinetics of CeO2 in the two-step process with CH4 as the reducing agent and CO2 as the oxidizing agent was investigated in an original prototype solar thermogravimetric reactor equipped with a parabolic dish solar concentrator. In particular, the ceria reduction and re-oxidation reactions were carried out under isothermal conditions. Several solid-state kinetic models based on reaction order, nucleation, shrinking core, and diffusion were utilized for deducing the reaction mechanisms. It was observed that both ceria reduction with CH4 and re-oxidation with CO2 were best represented by a 2D nucleation and nuclei growth model under the applied conditions. The kinetic models exhibiting the best agreement with the experimental reaction data were used to estimate the kinetic parameters. The values of apparent activation energies (~80 kJ·mol−1 for reduction and ~10 kJ·mol−1 for re-oxidation) and pre-exponential factors (~2–9 s−1 for reduction and ~123–253 s−1 for re-oxidation) were obtained from the Arrhenius plots.

Utilization of Low Wavelength Laser Linking with Electrochemical Etching to Produce Nano-Scale Porous Layer on p-Type Silicon Wafer with High Luminous Flux

2021 ◽  
Vol 10 (1) ◽  
pp. 016003
Author(s):  
Philip Nathaniel Immanuel ◽  
Chao-Ching Chiang ◽  
Tien-Hsi Lee ◽  
Sikkanthar Diwan Midyeen ◽  
Song-Jeng Huang
Keyword(s):  
Silicon Wafer ◽  
Porous Layer ◽  
Electrochemical Etching ◽  
Luminous Flux ◽  
Nano Scale ◽  
Type Silicon ◽  
P Type

A Precision Alignment Method to <100> Direction on (110) Silicon Wafer

2001 ◽  
Author(s):  
Fan-Gang Tseng ◽  
Kai-Chen Chang
Keyword(s):  
Silicon Wafer ◽  
Crystal Orientation ◽  
Silicon Wafers ◽  
Innovative Approach ◽  
Alignment Accuracy ◽  
Alignment Method

Abstract This paper proposes a novel pre-etch method to determine the lt;100gt; direction on (110) silicon wafers for bulk etching. Series of circular windows were arranged in an arc of radius 48.9 mm, and bulk-etched to form hexagonal shapes for crystal orientation finding. The corners of the hexagons can be used as an alignment reference for the indication of the lt;100gt; direction on (110) silicon wafers. This innovative approach has been demonstrated experimentally to give an orientation-alignment accuracy of ± 0.03° for (110) wafers with 4-inch diameter.

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