Novel Chain Stack Capacitor for 32Mb FeRAM and Beyond

ABSTRACTFor high density FeRAM devices small cell sizes are essential. The combination of the capacitor on plug (COP) structure with the Chain FeRAM™ cell design is used to develop a 32Mb FeRAM. Based on a 0.2 μm standard CMOS process a silicide capped polysilicon plug is used to contact the bottom electrode of the ferroelectric capacitor to the transistor. The barrier contact to the plug is formed by IrO2/Ir and a sputter deposited PZT (40/60) is used as ferroelectric material. The function of SrRuO3 (SRO) layers at the electrode/PZT interfaces is described in more detail. Double sided SRO results in slightly lower coercive voltage and imprint behavior compared to capacitors without SRO. Double sided SRO is essential to achieve excellent fatigue behavior measured up to 1×1011 switching cycles.

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Impact of Backend Processing on Integrated Ferroelectric Capacitor Characteristics

MRS Proceedings ◽

10.1557/proc-310-151 ◽

1993 ◽

Vol 310 ◽

Cited By ~ 13

Author(s):

P.D. Maniar ◽

R. Moazzami ◽

R.E. Jones ◽

A.C. Campbell ◽

C.J. Mogab

Keyword(s):

Leakage Current ◽

Sol Gel ◽

Low Pressure ◽

Cmos Process ◽

Ferroelectric Capacitor ◽

Standard Cmos Process ◽

Order Of Magnitude ◽

Pressure Hydrogen

AbstractIntegration of a ferroelectric capacitor module in a standard CMOS process subjects the ferroelectric to various ambients during backend processing, some of which can render the ferroelectric essentially non-operational for NVRAM applications. Post-crystallization processing of sol-gel deposited integrated ferroelectric PZT capacitors in the presence of hydrogen-containing, reducing ambients is observed to degrade the nonvolatile polarization. Low-pressure hydrogen anneals at temperatures as low as 200°C substantially degrade the nonvolatile polarization while the DRAM polarization remains roughly constant. Leakage current drops by one order of magnitude and fatigue is accelerated. A ferroelectric capacitor module can be integrated with minimal degradation with careful modifications in the backend processing.

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High performance radiation hardened register cell design on standard CMOS process

2003 IEEE Conference on Electron Devices and Solid-State Circuits (IEEE Cat. No.03TH8668) ◽

10.1109/edssc.2003.1283584 ◽

2004 ◽

Cited By ~ 3

Author(s):

Weizhong Wang

Keyword(s):

High Performance ◽

Cmos Process ◽

Cell Design ◽

Standard Cmos Process ◽

Radiation Hardened

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Dual-bottom-electrode CMUT based on standard CMOS process

2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems ◽

10.1109/nems.2011.6017285 ◽

2011 ◽

Author(s):

Ting Yu ◽

Xingqiang Lu ◽

Fengqi Yu

Keyword(s):

Bottom Electrode ◽

Cmos Process ◽

Standard Cmos Process

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Design of high density one time programmable memory in standard CMOS process

10.14711/thesis-b1070083 ◽

2009 ◽

Author(s):

Kwok Ping Ng

Keyword(s):

High Density ◽

Cmos Process ◽

Standard Cmos Process

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A 4-transistor static memory cell design with a standard CMOS process

10.1109/iscas.1989.100317 ◽

2003 ◽

Author(s):

Y. Ni ◽

F. Devos

Keyword(s):

Memory Cell ◽

Cmos Process ◽

Cell Design ◽

Standard Cmos Process

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Fabrication of Monolithic Integrated Bimaterial Resonant Uncooled IR Sensor

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.543.176 ◽

2013 ◽

Vol 543 ◽

pp. 176-179 ◽

Cited By ~ 1

Author(s):

D.Q. Zhao ◽

Xia Zhang ◽

P. Liu ◽

F. Yang ◽

C. Lin ◽

...

Keyword(s):

Silicon Nitride ◽

Hole Mobility ◽

Micro Electro Mechanical System ◽

Cmos Process ◽

Standard Cmos Process ◽

Ir Sensor ◽

Cantilever Structure ◽

Cmos Mems ◽

On Chip ◽

Micro Cantilever

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.

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