A 4-transistor static memory cell design with a standard CMOS process

2003 ◽  
Author(s):  
Y. Ni ◽  
F. Devos
2015 ◽  
Vol 62 (8) ◽  
pp. 2517-2523 ◽  
Author(s):  
Cong Li ◽  
Jian-Cheng Li ◽  
Jing Shang ◽  
Wen-Xiao Li ◽  
Shun-Qiang Xu

2002 ◽  
Vol 748 ◽  
Author(s):  
R. Bruchhaus ◽  
T. Ozaki ◽  
U. Ellerkmann ◽  
J. Lian ◽  
Y. Kumura ◽  
...  

ABSTRACTFor high density FeRAM devices small cell sizes are essential. The combination of the capacitor on plug (COP) structure with the Chain FeRAM™ cell design is used to develop a 32Mb FeRAM. Based on a 0.2 μm standard CMOS process a silicide capped polysilicon plug is used to contact the bottom electrode of the ferroelectric capacitor to the transistor. The barrier contact to the plug is formed by IrO2/Ir and a sputter deposited PZT (40/60) is used as ferroelectric material. The function of SrRuO3 (SRO) layers at the electrode/PZT interfaces is described in more detail. Double sided SRO results in slightly lower coercive voltage and imprint behavior compared to capacitors without SRO. Double sided SRO is essential to achieve excellent fatigue behavior measured up to 1×1011 switching cycles.


2013 ◽  
Vol 543 ◽  
pp. 176-179 ◽  
Author(s):  
D.Q. Zhao ◽  
Xia Zhang ◽  
P. Liu ◽  
F. Yang ◽  
C. Lin ◽  
...  

In this work we studied the fabrication of a monolithic bimaterial micro-cantilever resonant IR sensor with on-chip drive circuits. The effects of high temperature process and stress induced performance degradation were investigated. The post-CMOS MEMS (micro electro mechanical system) fabrication process of this IR sensor is the focus of this paper, starting from theoretical analysis and simulation, and then moving to experimental verification. The capacitive cantilever structure was fabricated by surface micromachining method, and drive circuits were prepared by standard CMOS process. While the stress introduced by MEMS films, such as the tensile silicon nitride which works as a contact etch stopper layer for MOSFETs and releasing stop layer for the MEMS structure, increases the electron mobility of NMOS, PMOS hole mobility decreases. Moreover, the NMOS threshold voltage (Vth) shifts, and transconductance (Gm) degrades. An additional step of selective removing silicon nitride capping layer and polysilicon layer upon IC area were inserted into the standard CMOS process to lower the stress in MOSFET channel regions. Selective removing silicon nitride and polysilicon before annealing can void 77% Vth shift and 86% Gm loss.


2012 ◽  
Vol 11 (04) ◽  
pp. 1240024 ◽  
Author(s):  
N. JOUVET ◽  
M. A. BOUNOUAR ◽  
S. ECOFFEY ◽  
C. NAUENHEIM ◽  
A. BEAUMONT ◽  
...  

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.


Author(s):  
M. Fischer ◽  
M. Nagele ◽  
D. Eichner ◽  
C. Schollhorn ◽  
R. Strobel

2010 ◽  
Vol 18 (21) ◽  
pp. 22215 ◽  
Author(s):  
Gun-Duk Kim ◽  
Hak-Soon Lee ◽  
Chang-Hyun Park ◽  
Sang-Shin Lee ◽  
Boo Tak Lim ◽  
...  

2018 ◽  
Vol E101.C (7) ◽  
pp. 574-580
Author(s):  
Koichi IIYAMA ◽  
Takeo MARUYAMA ◽  
Ryoichi GYOBU ◽  
Takuya HISHIKI ◽  
Toshiyuki SHIMOTORI

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