scholarly journals Dynamic threshold voltage control for dual supply voltage scheme on PD-SOI

2006 ◽  
Vol 3 (21) ◽  
pp. 453-458 ◽  
Author(s):  
Masaaki Iijima ◽  
Kenji Hamada ◽  
Masayuki Kitamura ◽  
Masahiro Numa ◽  
Akira Tada ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Supply Voltage ◽  
Voltage Control ◽  
Dynamic Threshold

Total dose behavior of partially depleted SOI dynamic threshold voltage MOS (DTMOS) for very low supply voltage applications (0.6-1 V)

2000 ◽  
Vol 47 (3) ◽  
pp. 613-619 ◽  
Author(s):  
V. Ferlet-Cavrois ◽  
P. Paillet ◽  
O. Musseau ◽  
J.L. Leray ◽  
O. Faynot ◽  
...  
Keyword(s):  
Total Dose ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Dynamic Threshold ◽  
Low Supply Voltage

49.3: Oxide TFT Scan Driver with Dynamic Threshold Voltage Control

2011 ◽  
Vol 42 (1) ◽  
pp. 718-721 ◽  
Author(s):  
Yong-Sung Park ◽  
Bo-Yong Chung ◽  
Chul-Kyu Kang ◽  
Seoung-Il Park ◽  
Ki-Ju Im ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Voltage Control ◽  
Dynamic Threshold ◽  
Oxide Tft

A Robust High Density 7T Subthreshold SRAM Bitcell with Partial Dynamic Threshold Voltage Connection Scheme

2011 ◽  
Vol 121-126 ◽  
pp. 1279-1285 ◽  
Author(s):  
Jun Yang ◽  
Ming Qiang Qiu ◽  
Kai Huang ◽  
Na Bai
Keyword(s):  
Standard Deviation ◽  
Threshold Voltage ◽  
Supply Voltage ◽  
Process Variation ◽  
High Density ◽  
Dynamic Threshold ◽  
Static Noise Margin ◽  
Noise Margin ◽  
Reduction Of Area ◽  
Static Noise

Combined with partial dynamic threshold MOSFET connection scheme, a high density 7T subthreshold SRAM bitcell operating at supply voltage of 200 mV is proposed in this paper. Dual write and single read ensures high read static noise margin of the SRAM bitcell without expense of writability degradation. The 7T SRAM exhibits robust efficiency, making the design less vulnerable to process variation. Compared to the referenced 6T and the 8T SRAM bitcell, the proposed bitcell has four aspects of improvement: (1) 5.1% and 6.1% larger hold margin, (2) 80.6% and 85.5% of standard deviation, (3) 50% and 18% reduction of area (at 200 mV), and (4) 16X and 32X bitcells per bitline. To our best knowledge, the area penalty of proposed SRAM is the smallest with robustness and functionality of subthreshold SRAM achieved.

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