Ultra low power supply voltage (0.3 V) operation with extreme high speed using bulk dynamic threshold voltage MOSFET (B-DTMOS) with advanced fast-signal-transmission shallow well

Author(s):  
A. Shibata ◽  
T. Matsuoka ◽  
S. Kakimoto ◽  
H. Kotaki ◽  
M. Nakano ◽  
...  
2015 ◽  
Vol 51 (23) ◽  
pp. 1914-1916 ◽  
Author(s):  
Daiguo Xu ◽  
Shiliu Xu ◽  
Guangbing Chen

2006 ◽  
Vol 41 (10) ◽  
pp. 2344-2353 ◽  
Author(s):  
J. Chen ◽  
L.T. Clark ◽  
T.-H. Chen

1993 ◽  
Vol 29 (15) ◽  
pp. 1324 ◽  
Author(s):  
L.E. Larson ◽  
M.M. Matloubian ◽  
J.J. Brown ◽  
A.S. Brown ◽  
M. Thompson ◽  
...  

Author(s):  
Kanan Bala Ray ◽  
Sushanta Kumar Mandal ◽  
Shivalal Patro

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>


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