A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells

2018 ◽  
Vol E101.C (4) ◽  
pp. 197-205
Author(s):  
Tohru KANEKO ◽  
Yuya KIMURA ◽  
Masaya MIYAHARA ◽  
Akira MATSUZAWA
1992 ◽  
Vol 27 (9) ◽  
pp. 1270-1276 ◽  
Author(s):  
A.M. Durham ◽  
W. Redman-White ◽  
J.B. Hughes

Electronics ◽  
2021 ◽  
Vol 10 (22) ◽  
pp. 2773
Author(s):  
Moo-Yeol Choi ◽  
Bai-Sun Kong

A linearity enhancement scheme for voltage-controlled oscillator (VCO)-based continuous-time (CT) delta-sigma (ΔΣ) analog-to-digital converters (ADCs) is proposed. Unlike conventional input feedforwarding techniques, the proposed feedforwarding scheme using digital feedback residue quantization (DFRQ) can avoid the analog summing amplifier, allow intrinsic anti-aliasing filtering (AAF) characteristic, and cause no switching noise injection into the input. A VCO-based CT ΔΣ ADC adapting the proposed DFRQ enables residue-only processing in the quantizer, avoiding the degradation of signal-to-noise and distortion ratio (SNDR) due to VCO nonlinearity. The use of DFRQ also reduces the voltage swing of integrators without the drawbacks caused by conventional input feedforwarding techniques. The performance evaluation results indicate that the proposed VCO-based CT ΔΣ ADC with DFRQ provides 30.3-dB SNDR improvement, reaching up to 83.5-dB in 2-MHz signal bandwidth.


Author(s):  
Lucien Breems ◽  
Muhammed Bolatkale ◽  
Hans Brekelmans ◽  
Shagun Bajoria ◽  
Jan Niehof ◽  
...  
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