Low-Power Fifth-Order Butterworth OTA-C Low-Pass Filter with an Impedance Scaler for Portable ECG Applications

2018 ◽  
Vol E101.C (12) ◽  
pp. 942-952
Author(s):  
Shuenn-Yuh LEE ◽  
Cheng-Pin WANG ◽  
Chuan-Yu SUN ◽  
Po-Hao CHENG ◽  
Yuan-Sun CHU
2016 ◽  
Vol 26 (03) ◽  
pp. 1750048 ◽  
Author(s):  
Vida Orduee Niar ◽  
Gholamreza Zare Fatin

In this paper, a [Formula: see text]-[Formula: see text] low-pass and low power filter with tunable in-band attenuation for WiMAX/LTE receiver is presented. The fourth-order filter consists of two cascaded biquad stages. The source-follower (SF) stage is used as a key building block in these biquads. In this paper, we have presented a circuit technique to reduce the nonlinearity of the SF stage resulting from unmatched signal swings at the gate and source terminals of the input transistor. The proposed SF stage, is used for design of a linear biquad which is then utilized in a fourth-order Butterworth low-pass filter. The simulation results of the filter for bandwidth of 10 MHz show that the IIP3 of the filter is equal to 8.22[Formula: see text]dBm, in-band noise density is 100[Formula: see text]nV/[Formula: see text]Hz and power consumption is 5.9[Formula: see text]mW. The supply voltage of the filter is equal to 1[Formula: see text]V.


2011 ◽  
Vol 32 (9) ◽  
pp. 095002 ◽  
Author(s):  
Zheng Gong ◽  
Bei Chen ◽  
Xueqing Hu ◽  
Yin Shi ◽  
Fa Foster Dai

Author(s):  
A. G. Zinovev ◽  
I. A. Shestakov

A method for measuring the self-capacitance, inductance, loss resistance, and Q-factor of inductors as part of an LC low-pass filter at its operating frequency is presented. An example of the practical application of this method for measuring the equivalent pa-rameters of inductors and capacitors as part of a fifth-order Cauer low-pass filter using network analyzer.


Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.


Author(s):  
Heba El-Halabi ◽  
Soubhi Abou-Chahine ◽  
Darine Kaddour ◽  
Emmanuel Pistono ◽  
Philippe Ferrari

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