Study of power line communication modems for automotive communication networks

Power line communication (PLC) technology has become very attractive in the automotive sector. As vehicle manufacturers aim to produce vehicles with improved fuel economy, comfort and technology, they are limited by current vehicle communication networks due to increased bulk and complexity. PLC technology has been suggested as a solution for this issue by utilizing existing power wires as a communication channel. However reliability is a big challenge with PLC technology, especially with critical systems such as braking, steering and engine control. This thesis studies the feasibility, reliability and possible improvements of PLC for controlling vehicle subsystems such as heating, ventilation and air conditioning (HVAC) system. In order to determine feasibility, several modems were examined for cost and ease of implementation. After selecting a modem solution, the PLC prototype modem was tested on an HVAC system test bed to control various fans, blowers and pumps over a DC power line. The PLC solution was then tested using a 2003 Ford Focus ZTS and a 2011 Ford Edge SE. The tests consisted of repeatedly sending a code from a transmitter connected to the vehicle battery while a receiver was connected to a power port inside the vehicle. The tests were run in several vehicle states e.g. Off, electronics on engine off and engine idle. The results from the tests showed that communication can be established over a vehicle power line with reasonable cost and ease. However reliability of the proposed solution needs to be improved before it can be implemented in vehicles. To improve performance of the proposed PLC solution, an impedance matching network for PLC was proposed. From current research an adaptive matching network utilizing active inductors and capacitor banks was designed and simulated. The designed matching network was simulated with several different automotive loads such as a vehicle battery and various lights. Simulations results showed the proposed matching network was capable of matching impedances with all the simulated automotive loads. When the circuit was built up and tested, there were issues with stability and cost of construction. The results show that more work needs to be done before PLC can become a suitable solution in vehicle communication network. With improvements such as impedance matching, line drive ability and robust modulation schemes, it won't be long before PLC will be a viable vehicle network solution.

CMOS active inductors and transformers for wireless applications

This thesis first reviews existing work in CMOS active inductors focusing on two implementations, Wu gyrator-C and differential floating active inductors. It then proposes a new method of quantifying the performance of active inductors by introducing a figure of merit called "mean quality factor" that is better suited to the large signal behavior of active inductors. New CMOS constant-Q active inductors are proposed that are intended specifically for applications where a large signal operation in required. The thesis then proposes CMOS active transformers that are active circuit equivalents of two magnetically coupled coils. Four applications of constant-Q active inductors and active transformers namely a 2.4 GHz voltage-controlled oscillator with -119.5dBc/Hz phase noise at 1 MHz offset, a 2.4 GHz current-mode phase-locked loop with -116dBc/Hz phase noise at 1 MHz offset and 80ns lock time, a 5 MHz 100X oversampled current-mode sigma-delta modulator with 50dB dynamic range and 65dB SNR, and a 1.6 GHz QPSK phase modulator with -101dBc/Hz phase noise at 1 MHz offset are presented.

Study of power line communication modems for automotive communication networks

Power line communication (PLC) technology has become very attractive in the automotive sector. As vehicle manufacturers aim to produce vehicles with improved fuel economy, comfort and technology, they are limited by current vehicle communication networks due to increased bulk and complexity. PLC technology has been suggested as a solution for this issue by utilizing existing power wires as a communication channel. However reliability is a big challenge with PLC technology, especially with critical systems such as braking, steering and engine control. This thesis studies the feasibility, reliability and possible improvements of PLC for controlling vehicle subsystems such as heating, ventilation and air conditioning (HVAC) system. In order to determine feasibility, several modems were examined for cost and ease of implementation. After selecting a modem solution, the PLC prototype modem was tested on an HVAC system test bed to control various fans, blowers and pumps over a DC power line. The PLC solution was then tested using a 2003 Ford Focus ZTS and a 2011 Ford Edge SE. The tests consisted of repeatedly sending a code from a transmitter connected to the vehicle battery while a receiver was connected to a power port inside the vehicle. The tests were run in several vehicle states e.g. Off, electronics on engine off and engine idle. The results from the tests showed that communication can be established over a vehicle power line with reasonable cost and ease. However reliability of the proposed solution needs to be improved before it can be implemented in vehicles. To improve performance of the proposed PLC solution, an impedance matching network for PLC was proposed. From current research an adaptive matching network utilizing active inductors and capacitor banks was designed and simulated. The designed matching network was simulated with several different automotive loads such as a vehicle battery and various lights. Simulations results showed the proposed matching network was capable of matching impedances with all the simulated automotive loads. When the circuit was built up and tested, there were issues with stability and cost of construction. The results show that more work needs to be done before PLC can become a suitable solution in vehicle communication network. With improvements such as impedance matching, line drive ability and robust modulation schemes, it won't be long before PLC will be a viable vehicle network solution.

CMOS active inductors and transformers for wireless applications

This thesis first reviews existing work in CMOS active inductors focusing on two implementations, Wu gyrator-C and differential floating active inductors. It then proposes a new method of quantifying the performance of active inductors by introducing a figure of merit called "mean quality factor" that is better suited to the large signal behavior of active inductors. New CMOS constant-Q active inductors are proposed that are intended specifically for applications where a large signal operation in required. The thesis then proposes CMOS active transformers that are active circuit equivalents of two magnetically coupled coils. Four applications of constant-Q active inductors and active transformers namely a 2.4 GHz voltage-controlled oscillator with -119.5dBc/Hz phase noise at 1 MHz offset, a 2.4 GHz current-mode phase-locked loop with -116dBc/Hz phase noise at 1 MHz offset and 80ns lock time, a 5 MHz 100X oversampled current-mode sigma-delta modulator with 50dB dynamic range and 65dB SNR, and a 1.6 GHz QPSK phase modulator with -101dBc/Hz phase noise at 1 MHz offset are presented.

Current-mode techniques for UWB frequency synthesizers

This thesis deals with current-mode techniques for ultra-wide band applications. An overview of ultra-wide band (UWB) wireless communications is presented. Two standards for UWB data communications, namely direct-synthesis UWB (DS-UWB) and Multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB are presented. MB-OFDM UWB devices must hop among 14 UWB channels within 9.5 ns, imposing stringent constraints on design of frequency synthesizers. A review of the state-of-the-art frequency synthesizers for MB-OFDM UWB applications is provided. Current-mode phase-locked loops with active inductors and active transformers employed in both loop filters and voltage-controlled oscillators are proposed and their performance in analyzed. Current-mode phase-locked loops decouple the PLL dynamic range from the scaling down of the supply voltage. An active-inductor VCO with both coarse and fine frequency adjustment, a hybrid VCO with a step-down passive transformer loaded with an active inductor, and a hybrid VCO with a step-down passive transformer with a varactor are proposed and their performances are analyzed. These VCOs obtain wide frequency tuning ranges without relying on switched back networks. To meet the timing constraint of UWB frequency synthesizers, Current-mode techniques are further developed for UWB frequency synthesizers. An active inductor with a bank of switched capacitors is proposed to provide fast locking. The bank of switched capacitors eliminates the frequency acquisition locking time of the frequency synthesizer, allowing 9.5 ns phase locking time. The proposed current-mode phase-locked loops, active-inductors oscillators and hybrid oscillators were designed and implemented in TSMC-0.18 μm and IBM-0.13 μm CMOS technologies.

Current-mode techniques for UWB frequency synthesizers

This thesis deals with current-mode techniques for ultra-wide band applications. An overview of ultra-wide band (UWB) wireless communications is presented. Two standards for UWB data communications, namely direct-synthesis UWB (DS-UWB) and Multi-band orthogonal frequency division multiplexing (MB-OFDM) UWB are presented. MB-OFDM UWB devices must hop among 14 UWB channels within 9.5 ns, imposing stringent constraints on design of frequency synthesizers. A review of the state-of-the-art frequency synthesizers for MB-OFDM UWB applications is provided. Current-mode phase-locked loops with active inductors and active transformers employed in both loop filters and voltage-controlled oscillators are proposed and their performance in analyzed. Current-mode phase-locked loops decouple the PLL dynamic range from the scaling down of the supply voltage. An active-inductor VCO with both coarse and fine frequency adjustment, a hybrid VCO with a step-down passive transformer loaded with an active inductor, and a hybrid VCO with a step-down passive transformer with a varactor are proposed and their performances are analyzed. These VCOs obtain wide frequency tuning ranges without relying on switched back networks. To meet the timing constraint of UWB frequency synthesizers, Current-mode techniques are further developed for UWB frequency synthesizers. An active inductor with a bank of switched capacitors is proposed to provide fast locking. The bank of switched capacitors eliminates the frequency acquisition locking time of the frequency synthesizer, allowing 9.5 ns phase locking time. The proposed current-mode phase-locked loops, active-inductors oscillators and hybrid oscillators were designed and implemented in TSMC-0.18 μm and IBM-0.13 μm CMOS technologies.

A 10 Gbps 4-PAM CMOS serial link transmitter with pre-emphasis

This thesis presents the design of 10 Gbps 4-PAM CMOS serial link transmitters. A new area-power efficient fully differential CMOS current-mode serial link transmitter with a proposed 2/4-PAM signaling configuration and a new pre-emphasis scheme is presented. The pre-emphasis inthe analog domain and the use of de-emphasis approach decres pre-emphasis power and chip area. The high-speed operation of the transmitter is achieved from the small voltage swing of critical nodes of the transmitter, shunt peaking with active inductors, multiplexing-at-input approach, the distributed multiplexing nodes, and the low characteristic impedance of the channels. The fully differential and bidirectional current-mode signaling minimizes the noise injected to the power and ground rails and the electromagnetic interference exerted from the channels to neighboring devices. A PLL containing a proposed five-stage VCO is implemented to generate multi-phase on -chip clocks. The proposed VCO minimized the phase noise by keeping a constant rising and falling time. Simulation results demonstrate that the current received at the far end of a 10 cm FR-4 microstriop has a 4-PAM current eye width of 185 ps and eye hight of 1.21 mA. It consumes 57.6 mW power with differnetial delay block, or 19.2 mW power with inverter buffer chain. The total transistor area of the transmitter is 26.845 ....excluding the delay block.