Well-Structured Modified Booth Multiplier and Its Application to Reconfigurable MAC Design

2011 ◽  
Vol E94-C (6) ◽  
pp. 1112-1119 ◽  
Author(s):  
Li-Rong WANG ◽  
Ming-Hsien TU ◽  
Shyh-Jye JOU ◽  
Chung-Len LEE
Keyword(s):  
Booth Multiplier

scholarly journals Radix-16 Booth multiplier using novel weighted 2-stage Booth algorithm

2014 ◽  
Vol 11 (13) ◽  
pp. 20140407-20140407 ◽  
Author(s):  
Hyunpil Kim ◽  
Sangook Moon ◽  
Yongsurk Lee
Keyword(s):  
Booth Multiplier

ACBAM - Accuracy Configurable Sign Inclusive Broken Array Booth Multiplier Design

2021 ◽  
pp. 1-1
Author(s):  
Avishek Sinharoy ◽  
Hardik Agrawal ◽  
Anindya Sundar Dhar
Keyword(s):  
Booth Multiplier

scholarly journals Design of delay efficient Booth multiplier using pipelining

2018 ◽  
Vol 7 (2.16) ◽  
pp. 94
Author(s):  
Abhishek Choubey ◽  
SPV Subbarao ◽  
Shruti B. Choubey
Keyword(s):  
Critical Path ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Digital Signal ◽  
Path Delay ◽  
Large Area ◽  
Booth Multiplier ◽  
Critical Path Delay ◽  
Long Latency ◽  
Comparison Results

Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier. 

scholarly journals VLSI implementation of Wallace Tree Multiplier using Ladner-Fischer Adder

2021 ◽  
Vol 14 (1) ◽  
pp. 22-31
Author(s):  
Kommalapati Monica ◽  
◽  
Dereddy Anuradha ◽  
Syed Rasheed ◽  
Barnala Shereesha ◽  
...  
Keyword(s):  
Power Consumption ◽  
Field Programmable Gate Array ◽  
Finite Impulse Response ◽  
Research Work ◽  
Industrial Applications ◽  
Booth Multiplier ◽  
Wallace Tree ◽  
Look Up Table ◽  
Field Programmable ◽  
Wallace Tree Multiplier

Nowadays, most of the application depends on arithmetic designs such as an adder, multiplier, divider, etc. Among that, multipliers are very essential for designing industrial applications such as Finite Impulse Response, Fast Fourier Transform, Discrete cosine transform, etc. In the conventional methods, different kind of multipliers such as array multiplier, booth multiplier, bough Wooley multiplier, etc. are used. These existing multipliers are occupied more area to operate. In this study, Wallace Tree Multiplier (WTM) is implemented to overcome this problem. Two kinds of multipliers have designed in this research work for comparison. At first, existing WTM is designed with normal full adders and half adders. Next, proposed WTM is designed using Ladner Fischer Adder (LFA) to improve the hardware utilization and reduce the power consumption. Field Programmable Gate Array (FPGA) performances such as slice Look Up Table (LUT), Slice Register, Bonded Input-Output Bios (IOB) and power consumption are evaluated. The proposed WTM-LFA architecture occupied 374 slice LUT, 193 slice register, 59 bonded IOB, and 26.31W power. These FPGA performances are improved compared to conventional multipliers such asModified Retiming Serial Multiplier (MRSM), Digit Based Montgomery Multiplier (DBMM), and Fast Parallel Decimal Multiplier (FPDM).

scholarly journals Design of Booth Multiplier using Double Gate MOSFET

2017 ◽  
Vol 167 (4) ◽  
pp. 19-23
Author(s):  
Yogeesh K.V. ◽  
Venkateshkumar H.
Keyword(s):  
Double Gate ◽  
Booth Multiplier ◽  
Double Gate Mosfet

scholarly journals Designing of a reversible fault tolerant booth multiplier

2018 ◽  
Vol 53 (3) ◽  
pp. 199-204
Author(s):  
Md M Rahman ◽  
Md M Hossain ◽  
Lafifa Jamal ◽  
S Nowrin
Keyword(s):  
Fault Tolerant ◽  
Quantum Cost ◽  
Input Output ◽  
Booth Multiplier ◽  
Output Mapping ◽  
Result Analysis ◽  
Cost Parameters

Conventional logic dissipates more power by losing bits of information whereas reversibility recovers bit loss from the unique input-output mapping. This paper presents the design of a reversible fault tolerant booth multiplier which can multiply both signed and unsigned numbers. The proposed circuit tolerant designed using only fault tolerant reversible gates. Thus the entire scheme inherently becomes fault tolerant. Several theorems on the numbers of gates, garbage outputs, quantum cost of the proposed design have been presented to show the efficiency of the design. The result analysis shows that the proposed design is optimized in terms of all cost parameters. The simulation of the proposed circuit verifies the correctness of the circuit.Bangladesh J. Sci. Ind. Res.53(3), 199-204, 2018

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