Low Power Pulse Generator Design Using Hybrid Logic

The present research paper proposes to implement a low power pulse-triggered flip-flop. The proposed design is MHLFF (modified hybrid latch flip-flop). In MHLFF method, the pulse generator will be altered concerning illustration inverters what’s more a pasquinade transistor. This technique will be comparative should understood kind about flip flop what’s more it utilizes a static lock structure. Should succeed Most exceedingly bad situation delay issue brought on Eventually Tom's perusing discharging way comprise from claiming three stacked transistor MHLFF may be presented. We can minimize the power and delay when compared to the existing models i.e, CDFF and SCDFF. The circuit was implementing using Cadence Virtuoso tool in 90-nm and 45-nm technology.

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A Cost Effective Low Power Pulse Generator for UWB Medical Applications

2018 International Conference on Applied Electromagnetics, Signal Processing and Communication (AESPC) ◽

10.1109/aespc44649.2018.9033298 ◽

2018 ◽

Author(s):

Shilpi Ruchi Kerketta ◽

Debalina Ghosh

Keyword(s):

Low Power ◽

Pulse Generator ◽

Cost Effective ◽

Medical Applications ◽

Power Pulse

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Ultra low power pulse generator based on a ring oscillator with direct path current avoidance

2013 IEEE 4th Latin American Symposium on Circuits and Systems (LASCAS) ◽

10.1109/lascas.2013.6519036 ◽

2013 ◽

Cited By ~ 6

Author(s):

F. Veirano ◽

P. Perez ◽

S. Besio ◽

P. Castro ◽

F. Silveira

Keyword(s):

Low Power ◽

Pulse Generator ◽

Ring Oscillator ◽

Direct Path ◽

Ultra Low Power ◽

Power Pulse

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Low power pulse generator as a capacitive interface for MEMS applications

2009 Ph.D. Research in Microelectronics and Electronics ◽

10.1109/rme.2009.5201366 ◽

2009 ◽

Cited By ~ 2

Author(s):

Mohamad Al Kadi Jazairli ◽

Denis Flandre

Keyword(s):

Low Power ◽

Pulse Generator ◽

Power Pulse

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A COMPACT CMOS POWER-ON-RESET PULSE GENERATOR DESIGN WITH LOW-POWER AND WIDE OPERATION RANGE

Journal of Circuits System and Computers ◽

10.1142/s0218126610006876 ◽

2010 ◽

Vol 19 (06) ◽

pp. 1365-1380 ◽

Cited By ~ 1

Author(s):

SUAT U. AY

Keyword(s):

Low Power ◽

Pulse Generator ◽

Low Voltage ◽

Supply Voltage ◽

Cmos Process ◽

Detection Capability ◽

Voltage Range ◽

Low Voltage Operation ◽

Reset Pulse ◽

Generator Design

A compact power-on-reset pulse generator (POR-PG) circuit with a low-power and low-voltage operation capability is presented. Proposed POR-PG was fabricated in 0.5 μm 2P3M CMOS process. It was determined from simulations and measurements that proposed POR-PG works supply voltage levels between 1.8 V and 3.3 V and supply voltage rise times between 100 ns and 1 ms. POR-PG has very small silicon footprint. Layout size of proposed POR-PG circuit was 120 μm × 5 μm in 0.5 μm CMOS process. Comparing with other POR-PG circuits in the literature, proposed design enjoys lowest power consumption (< 6 μW), smallest silicon footprint, widest supply voltage range, and additional features such as brown-out detection capability. These achieved by using a unique cascadable POR delay element that consumes very low-power.

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