Low Noise Power Amplifier in 28-nm UTBB FDSOI Technology with Forward Body Bias

2018 ◽  
Vol 8 (2) ◽  
pp. 129-132
Author(s):  
Adnan Harb ◽  
Keyword(s):  
Power Amplifier ◽  
Low Noise ◽  
Noise Power ◽  
Forward Body Bias ◽  
28 Nm ◽  
Body Bias

A microwave switchable low-noise power amplifier for an active backscatter tag

2014 ◽  
Vol 56 (5) ◽  
pp. 1251-1255
Author(s):  
Jeremie Prades ◽  
Anthony Ghiotto ◽  
Thierry Taris ◽  
Nicolas Regimbal ◽  
Jean-Marie Pham ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Low Noise ◽  
Noise Power

scholarly journals A Low Noise Power Amplifier MMIC to Mitigate Co-Site Interference in 5G Front End Modules

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 124900-124909
Author(s):  
Neha Bajpai ◽  
Ahtisham Pampori ◽  
Paramita Maity ◽  
Manish Shah ◽  
Amitava Das ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Low Noise ◽  
Noise Power ◽  
Front End

scholarly journals An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1686
Author(s):  
Jian Chen ◽  
Wei Zhang ◽  
Qingqing Sun ◽  
Lizheng Liu
Keyword(s):  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Serial Link ◽  
Ldo Regulator ◽  
28 Nm

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

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