scholarly journals An 8–12.5-GHz LC PLL with Dual VCO and Noise-Reduced LDO Regulator for Multilane Multiprotocol SerDes in 28-nm CMOS Technology

Electronics ◽  
2021 ◽  
Vol 10 (14) ◽  
pp. 1686
Author(s):  
Jian Chen ◽  
Wei Zhang ◽  
Qingqing Sun ◽  
Lizheng Liu
Keyword(s):  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Serial Link ◽  
Ldo Regulator ◽  
28 Nm

This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves multiprotocol serial link coverage from 8 to 12.5 Gbps. Two switch capacitor array-based LC VCOs have a large frequency-tuning range and small VCO gain. The noise-reduced LDO regulator provides a very low-noise power supply to the VCO. The active area occupied by the proposed LC PLL in UMC 28-nm 1P10M complementary metal–oxide–semiconductor (CMOS) technology is 0.25 mm2. The phase noise of the VCO at 1 MHz is −108.1 dBc/Hz. The power consumption of the LC PLL with a 1.8-V supply is 16.5 mW.

A 52-to-67 GHz dual-core push–push VCO in 40-nm CMOS

2018 ◽  
Vol 10 (7) ◽  
pp. 783-793 ◽  
Author(s):  
Vadim Issakov ◽  
Johannes Rimmelspacher ◽  
Saverio Trotta ◽  
Marc Tiebout ◽  
Amelie Hagelauer ◽  
...  
Keyword(s):  
Continuous Wave ◽  
Frequency Tuning ◽  
Second Harmonic ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Chip Area ◽  
Wave Radar ◽  
Dual Core

AbstractWe present a continuously tunable 52-to-67 GHz push–push dual-core voltage-controlled oscillator (VCO) in a 40 nm bulk complementary metal–oxide–semiconductor (CMOS) technology. The circuit is suitable for 60 GHz frequency-modulated-continuous-wave radar applications requiring a continuously tunable ultra-wide modulation bandwidth. The LC-tank inductor is used to couple the two VCO cores. The fundamental frequency of the VCO can be tuned from 26 to 33.5 GHz, which corresponds to a frequency tuning range of 25%. The second harmonic is extracted in a non-invasive way using a transformer. The primary side acts simultaneously as a second harmonic filter. The VCO achieves in measurement a low phase noise of −91.8 dBc/Hz at 1 MHz offset at 62 GHz and an output power of −20 dBm. The VCO including buffers dissipates in the dual-core operation mode 60 mA from a single 1.1 V supply and consumes a chip area of 0.58 mm2.

A VERY LOW NOISE WIDEBAND CLASS-C CMOS LC VCO

2012 ◽  
Vol 21 (04) ◽  
pp. 1250033 ◽  
Author(s):  
FATEMEH ATAEI ◽  
MOHAMMAD YAVARI
Keyword(s):  
Phase Noise ◽  
Tuning Range ◽  
Capacitor Bank ◽  
Cmos Technology ◽  
Low Noise ◽  
Voltage Controlled Oscillator ◽  
Switching Scheme ◽  
Wide Tuning Range ◽  
New Class ◽  
Class C

In this paper, a new class-C voltage-controlled oscillator (VCO) is presented. In the proposed VCO, the tail capacitor of the conventional class-C oscillator is dislocated from the source of the cross-coupled transistors to their gate to achieve a rail-to-rail output swing. This improves the phase noise by 2.9 dB compared to the conventional class-C one. Besides, a new switching scheme is presented in the switched capacitor bank used for coarse tuning of the proposed VCO to lower the on resistance of the switches as well as to reduce the parasitic capacitors. This wide tuning range class-C VCO is designed in a 0.18 μm CMOS technology. It achieves a -125.3 dBc/Hz phase noise at 1 MHz offset from a 2.2 GHz carrier frequency while covering a wide tuning range from 1.82 to 2.65 GHz and consuming 3.5 mW power from a single 0.9 V power supply.

A 0.015-mm $^{\text{2}}$ Inductorless 32-GHz Clock Generator With Wide Frequency-Tuning Range in 28-nm CMOS Technology

2017 ◽  
Vol 64 (6) ◽  
pp. 655-659 ◽  
Author(s):  
Gyu-Seob Jeong ◽  
Wooseok Kim ◽  
Jaejin Park ◽  
Taeik Kim ◽  
Hojin Park ◽  
...  
Keyword(s):  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Clock Generator ◽  
28 Nm

scholarly journals Design of a very low-power, low-cost 60 GHz receiver front-end implemented in 65 nm CMOS technology

2011 ◽  
Vol 3 (2) ◽  
pp. 131-138 ◽  
Author(s):  
Michael Kraemer ◽  
Daniela Dragomirescu ◽  
Robert Plana
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Noise Figure ◽  
Low Cost ◽  
Cmos Technology ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Voltage Controlled Oscillator ◽  
60 Ghz ◽  
Front End

The research on the design of receiver front-ends for very high data-rate communication in the 60 GHz band in nanoscale Complementary Metal Oxide Semiconductor (CMOS) technologies is going on for some time now. Although a multitude of 60 GHz front-ends have been published in recent years, they are not consequently optimized for low power consumption. Thus, these front-ends dissipate too much power for battery-powered applications like handheld devices, mobile phones, and wireless sensor networks. This article describes the design of a direct conversion receiver front-end that addresses the issue of power consumption, while at the same time permitting low cost (due to area minimization by the use of spiral inductors). It is implemented in a 65 nm CMOS technology. The realized front-end achieves a record power consumption of only 43 mW including low-noise amplifier (LNA), mixer, a voltage controlled oscillator (VCO), a local oscillator (LO) buffer, and a baseband buffer (without this latter buffer the power consumption is even lower, only 29 mW). Its pad-limited size is 0.55 × 1 mm2. At the same time, the front-end achieves state-of-the-art performance with respect to its other properties: Its maximum measured power conversion gain is 30 dB, the RF and IF bandwidths are 56.5–61.5 and 0–1.5 GHz, respectively, its measured minimum noise figure is 9.2 dB, and its measured IP−1 dB is −36 dBm.

scholarly journals A LOW PHASE NOISE, POWER EFFICIENT VOLTAGE CONTROLLED OSCILLATOR USING 0.18-μM CMOS TECHNOLOGY

2014 ◽  
pp. 256-259
Author(s):  
AJIT SAMASGIKAR
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Tuning Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Noise Power ◽  
Voltage Controlled Oscillator ◽  
Power Efficient ◽  
Sustained Oscillations ◽  
Low Phase Noise

A low phase noise, power efficient VCO using UMC 0.18μm CMOS technology has been proposed in this paper. The proposed VCO has a tuning range of 9.71GHz to 9.9GHz, with a phase noise of -79.88 dBc/Hz @ 600kHz offset. The Vtune ranging between 1V - 1.5V generates sustained oscillations. The maximum power consumption of the VCO is 11.9mW using a supply voltage of 1.8V with ±10% variation.

scholarly journals RF CMOS Oscillators Design for autonomous Connected Objects

2019 ◽  
Vol 88 ◽  
pp. 05001
Author(s):  
Fayrouz Haddad ◽  
Wenceslas Rahajandraibe ◽  
Imen Ghorbel
Keyword(s):  
Performance Optimization ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Voltage Controlled Oscillator ◽  
Noise Performance ◽  
Ultra Low Power ◽  
Wireless Transceiver ◽  
Cmos Oscillators ◽  
Phase Noise Performance

Voltage controlled oscillator (VCO) is an integral part of IoT wireless transceiver components. In this paper, VCOs operating around 2.4 GHz have been designed in CMOS technology. The relation between their components and specifications is studied for their performance optimization. Ultra-low power, less than 270 µW, has been obtained, while performing a frequency tuning range of about 10% between 2.1 and 2.4 GHz. Investigations on phase noise performance have been also achieved.

scholarly journals CMOS RF Front-Ends For Bluetooth Applications

2021 ◽  
Author(s):  
Yanmei Li
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Control Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Added Efficiency ◽  
Common Gate ◽  
Offset Frequency

This project investigates the design of RF front-ends for bluetooth applications. The main objectives in each design are optimized noise figure, power consumption, gain and linearity. The designed cascode LNA achieves 1.37 dB low noise figure through ports matching and maximizes the voltage gain to 11.5 dB. The port isolation reaches to 82 dB. A 2 MHz low IF down-conversion mixer is developed. It employs current injection to reduce the flicker noise of MOSFETs. The total noise figure of the mixer is 17 dB and input referred IIP3 is 4.97 dB. A quadrature mixer constructed by two symmetric Gilbert mixers are discussed. A common-gate class E power amplifier is investigated. Through connecting a L matching network, the output power would be 17.7 dBm at 1.4 V power supply and the power added efficiency PAE and drain efficiency DE are 41% and 42.8 % respectively. To supply two LO frequencies with 90º phase difference, a quadrature voltage controlled oscillator is designed using a series of coupling structure and accumulation mode PMOS varactors. The frequency tuning range is 2.304 GHz ~ 2.54 GHz when the control voltage changes from 0 to 0.7 V. The QVCO exhibits phase noise of -113 dBc/Hz at 600 kHz offset frequency and -119 dBc.Hz at 1 MHz offset frequency. All the circuits were designed in TSMC-0.18μm 1.8 V CMOS technology and simulated using HSPICE RF simulator.

scholarly journals CMOS RF Front-Ends For Bluetooth Applications

2021 ◽  
Author(s):  
Yanmei Li
Keyword(s):  
Flicker Noise ◽  
Noise Figure ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Low Noise ◽  
Control Voltage ◽  
Voltage Controlled Oscillator ◽  
Power Added Efficiency ◽  
Common Gate ◽  
Offset Frequency

This project investigates the design of RF front-ends for bluetooth applications. The main objectives in each design are optimized noise figure, power consumption, gain and linearity. The designed cascode LNA achieves 1.37 dB low noise figure through ports matching and maximizes the voltage gain to 11.5 dB. The port isolation reaches to 82 dB. A 2 MHz low IF down-conversion mixer is developed. It employs current injection to reduce the flicker noise of MOSFETs. The total noise figure of the mixer is 17 dB and input referred IIP3 is 4.97 dB. A quadrature mixer constructed by two symmetric Gilbert mixers are discussed. A common-gate class E power amplifier is investigated. Through connecting a L matching network, the output power would be 17.7 dBm at 1.4 V power supply and the power added efficiency PAE and drain efficiency DE are 41% and 42.8 % respectively. To supply two LO frequencies with 90º phase difference, a quadrature voltage controlled oscillator is designed using a series of coupling structure and accumulation mode PMOS varactors. The frequency tuning range is 2.304 GHz ~ 2.54 GHz when the control voltage changes from 0 to 0.7 V. The QVCO exhibits phase noise of -113 dBc/Hz at 600 kHz offset frequency and -119 dBc.Hz at 1 MHz offset frequency. All the circuits were designed in TSMC-0.18μm 1.8 V CMOS technology and simulated using HSPICE RF simulator.

scholarly journals Performance Analysis of Ring Oscillators and Current-Starved VCO in 45-nm CMOS Technology

2022 ◽  
Vol 10 (1) ◽  
pp. 732-737
Author(s):  
Prakash Sharma
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Ring Oscillator ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Noise Power ◽  
Ring Oscillators ◽  
Voltage Controlled Oscillator

Abstract: This paper presents a relative study among two Ring oscillators architecture (CMOS, NMOS) and current-starved Voltage-controlled oscillator (CS-VCO) on the basis of different parameters like power dissipation ,phase noise etc. All the design has been done in 45- nm CMOS technology node and 2.3 GHz Centre frequency have been taken for the comparison because of their applications in AV Devices and Radio control. An inherent idea of the given performance parameters has been realize by thecomparative study. The comparative data shows that NMOS based Ring oscillator is good option in terms of the phase noise performance. In this study NMOS Ring Oscillator have attain a phase noise -97.94 dBc/Hz at 1 MHz offset frequency from 2.3 GHz center frequency. The related data also shows that CMOS Ring oscillator is the best option in terms of power consumption. In this work CMOS Ring oscillator evacuatea power of 1.73 mW which is quite low. Keywords: Voltage controlled oscillator (VCO), phase noise, power consumption, Complementary metal-oxide-semiconductor (CMOS), Current Starved Voltage-Controlled Oscillator (CS- VCO), Pull up network (PUN), Pull down network (PDN)

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