scholarly journals Achromaticity of the LC Modulator for 3D Applications

2015 ◽  
Vol 15 (3) ◽  
pp. 82-90 ◽  
Author(s):  
G. V. Simonenko ◽  
S. A. Studentsov ◽  
V. A. Ezhov
Keyword(s):  
Nanomaterials ◽  
2021 ◽  
Vol 11 (3) ◽  
pp. 600
Author(s):  
Cristina Bran ◽  
Jose Angel Fernandez-Roldan ◽  
Rafael P. del Real ◽  
Agustina Asenjo ◽  
Oksana Chubykalo-Fesenko ◽  
...  

Cylindrical magnetic nanowires show great potential for 3D applications such as magnetic recording, shift registers, and logic gates, as well as in sensing architectures or biomedicine. Their cylindrical geometry leads to interesting properties of the local domain structure, leading to multifunctional responses to magnetic fields and electric currents, mechanical stresses, or thermal gradients. This review article is summarizing the work carried out in our group on the fabrication and magnetic characterization of cylindrical magnetic nanowires with modulated geometry and anisotropy. The nanowires are prepared by electrochemical methods allowing the fabrication of magnetic nanowires with precise control over geometry, morphology, and composition. Different routes to control the magnetization configuration and its dynamics through the geometry and magnetocrystalline anisotropy are presented. The diameter modulations change the typical single domain state present in cubic nanowires, providing the possibility to confine or pin circular domains or domain walls in each segment. The control and stabilization of domains and domain walls in cylindrical wires have been achieved in multisegmented structures by alternating magnetic segments of different magnetic properties (producing alternative anisotropy) or with non-magnetic layers. The results point out the relevance of the geometry and magnetocrystalline anisotropy to promote the occurrence of stable magnetochiral structures and provide further information for the design of cylindrical nanowires for multiple applications.


Author(s):  
Francesco Pirotti ◽  
Maria Antonia Brovelli ◽  
Gabriele Prestifilippo ◽  
Giorgio Zamboni ◽  
Candan Eylul Kilsedar ◽  
...  

Geophysics ◽  
2016 ◽  
Vol 81 (3) ◽  
pp. Q27-Q40 ◽  
Author(s):  
Katrin Löer ◽  
Andrew Curtis ◽  
Giovanni Angelo Meles

We have evaluated an explicit relationship between the representations of internal multiples by source-receiver interferometry and an inverse-scattering series. This provides a new insight into the interaction of different terms in each of these internal multiple prediction equations and explains why amplitudes of estimated multiples are typically incorrect. A downside of the existing representations is that their computational cost is extremely high, which can be a precluding factor especially in 3D applications. Using our insight from source-receiver interferometry, we have developed an alternative, computationally more efficient way to predict internal multiples. The new formula is based on crosscorrelation and convolution: two operations that are computationally cheap and routinely used in interferometric methods. We have compared the results of the standard and the alternative formulas qualitatively in terms of the constructed wavefields and quantitatively in terms of the computational cost using examples from a synthetic data set.


2013 ◽  
pp. 207-230 ◽  
Author(s):  
Oliver Wang ◽  
Manuel Lang ◽  
Nikolce Stefanoski ◽  
Alexander Sorkine-Hornung ◽  
Olga Sorkine-Hornung ◽  
...  

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 000334-000346
Author(s):  
Chet Palesko ◽  
E. Jan Vardaman ◽  
Alan Palesko

2.5D and 3D applications using through silicon vias (TSVs) are increasingly being considered as a packaging alternative. Miniaturization and high performance product requirements are driving this move – even though in many cases the cost of both 2.5D and 3D is still high. The primary applications for 2.5D interposers with TSVs are GPUs/CPUs, high-end ASICs, and FPGAs. Adoption for FPGAs has already started. The key to the performance gains in recently introduced FPGAs is the partitioning of an FPGA die into four “slices” that are mounted on a silicon interposer or what Xilinx calls its Stacked Silicon Interconnect technology. Applications for interposers include tablets, gaming, and high-end computing and network systems. The drivers are mainly partitioning large die, integrating single chips into a module, reducing die size where substrate density is the constraint, and using the interposer to minimize the stress on large die that are fabricated with extra-low-k (ELK) dielectrics. The primary applications for 3D solutions are stacked memory cubes and memory plus logic. The true 3D nature of stacking all active silicon allows better miniaturization, but yield issues can quickly drive the cost unacceptably high. This analysis examines the cost drivers for 2.5D and 3D applications. Activity based cost models will be used to analyze the complete cost of fabricating and assembling active die on a silicon interposer and active die stacking on other active die. Total product cost impact - not just the cost of a specific activity - is the focus of this analysis. Since yields play a major role in cost, a sensitivity analysis of the different yields including die yield before wafer probe, die yield after wafer probe, TSV yield, interposer yield, assembly yield, substrate yield, etc. will be presented. The critical yield points in the manufacturing flow and dominant activity cost drivers (equipment, material, and /or labor) will be presented as well as suggested minimum thresholds for 2.5D and 3D technology to be a cost effective technology.


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