scholarly journals High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Author(s):  
Asep Muhamad Awaludin ◽  
Harashta Tatimma Larasati ◽  
Howon Kim

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1451
Author(s):  
Asep Muhamad Awaludin ◽  
Harashta Tatimma Larasati ◽  
Howon Kim

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.


2021 ◽  
Vol 2021 ◽  
pp. 1-8
Author(s):  
Yong Xiao ◽  
Weibin Lin ◽  
Yun Zhao ◽  
Chao Cui ◽  
Ziwen Cai

Teleoperated robotic systems are those in which human operators control remote robots through a communication network. The deployment and integration of teleoperated robot’s systems in the medical operation have been hampered by many issues, such as safety concerns. Elliptic curve cryptography (ECC), an asymmetric cryptographic algorithm, is widely applied to practical applications because its far significantly reduced key length has the same level of security as RSA. The efficiency of ECC on GF (p) is dictated by two critical factors, namely, modular multiplication (MM) and point multiplication (PM) scheduling. In this paper, the high-performance ECC architecture of SM2 is presented. MM is composed of multiplication and modular reduction (MR) in the prime field. A two-stage modular reduction (TSMR) algorithm in the SCA-256 prime field is introduced to achieve low latency, which avoids more iterative subtraction operations than traditional algorithms. To cut down the run time, a schedule is put forward when exploiting the parallelism of multiplication and MR inside PM. Synthesized with a 0.13 um CMOS standard cell library, the proposed processor consumes 341.98k gate areas, and each PM takes 0.092 ms.


2013 ◽  
pp. 562-583
Author(s):  
Michael Hutter ◽  
Erich Wenger ◽  
Markus Pelnar ◽  
Christian Pendl

In this chapter, the authors explore the feasibility of Elliptic Curve Cryptography (ECC) on Wireless Identification and Sensing Platforms (WISPs). ECC is a public-key based cryptographic primitive that has been widely adopted in embedded systems and Wireless Sensor Networks (WSNs). In order to demonstrate the practicability of ECC on such platforms, the authors make use of the passively powered WISP4.1DL UHF tag from Intel Research Seattle. They implemented ECC over 192-bit prime fields and over 191-bit binary extension fields and performed a Montgomery ladder scalar multiplication on WISPs with and without a dedicated hardware multiplier. The investigations show that when running at a frequency of 6.7 MHz, WISP tags that do not support a hardware multiplier need 8.3 seconds and only 1.6 seconds when a hardware multiplier is supported. The binary-field implementation needs about 2 seconds without support of a hardware multiplier. For the WISP, ECC over prime fields provides best performance when a hardware multiplier is available; binary-field based implementations are recommended otherwise. The use of ECC on WISPs allows the realization of different public-key based protocols in order to provide various cryptographic services such as confidentiality, data integrity, non-repudiation, and authentication.


Author(s):  
Michael Hutter ◽  
Erich Wenger ◽  
Markus Pelnar ◽  
Christian Pendl

In this chapter, the authors explore the feasibility of Elliptic Curve Cryptography (ECC) on Wireless Identification and Sensing Platforms (WISPs). ECC is a public-key based cryptographic primitive that has been widely adopted in embedded systems and Wireless Sensor Networks (WSNs). In order to demonstrate the practicability of ECC on such platforms, the authors make use of the passively powered WISP4.1DL UHF tag from Intel Research Seattle. They implemented ECC over 192-bit prime fields and over 191-bit binary extension fields and performed a Montgomery ladder scalar multiplication on WISPs with and without a dedicated hardware multiplier. The investigations show that when running at a frequency of 6.7 MHz, WISP tags that do not support a hardware multiplier need 8.3 seconds and only 1.6 seconds when a hardware multiplier is supported. The binary-field implementation needs about 2 seconds without support of a hardware multiplier. For the WISP, ECC over prime fields provides best performance when a hardware multiplier is available; binary-field based implementations are recommended otherwise. The use of ECC on WISPs allows the realization of different public-key based protocols in order to provide various cryptographic services such as confidentiality, data integrity, non-repudiation, and authentication.


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