An Area and Energy Efficient RAM Cell Design in Quantum Dot Cellular Automata

2019 ◽  
Vol 16 (10) ◽  
pp. 4179-4187
Author(s):  
Amanpreet Sandhu ◽  
Sheifali Gupta
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Short Channel ◽  
Quantum Dot Cellular Automata ◽  
Channel Effects

The Conventional Complementary Metal oxide semiconductor (CMOS) technology has been revolutionized from the past few decades. However, the CMOS circuit faces serious constraints like short channel effects, quantum effects, doping fluctuations at the nanoscale which limits them to further scaling down at nano meter range. Among various existing nanotechnologies, Quantum dot Cellular Automata (QCA) provides new solution at nanocircuit design. The technical advancement of the paper lies in designing a high performance RAM cell with less QCA cells, less occupational area and lower power dissipation characteristics. The design occupies 12.5% lower area, 16.6% lower input to output delay, and dissipates 18.26% lesser energy than the designs in the literature. The proposed RAMcell is robust due to lesser noise variations. Also it has less fabrication cost due to absence of rotated cells.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

Etching Effects of Nanotechnology Fabrication on CMOS Transistor Gate Wafer Manufacturing Process Integration

2010 ◽  
Vol 154-155 ◽  
pp. 938-941
Author(s):  
Chun Jen Weng
Keyword(s):  
Process Integration ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel Effects ◽  
Fabrication Technology ◽  
Short Channel ◽  
Channel Effects ◽  
Cmos Transistor ◽  
Scaling Down ◽  
Wafer Manufacturing

As wafer nanotechnology gate is scaling down, the fabrication technology of gate spacer for transistor becomes more critical in manufacturing processes. Because wafer fabrication technologies, sidewall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present study is to overcome the fabrication processes limitations and proposed modified feasible etching processes integration on the formation processing for complementary metal oxide semiconductor nanofabrication process of gate spacer technology and electrical characteristics.

A Step Towards Optimisation of 2 to 4 Decoder Using Farooq-Nikesh-Zaid Gate with Coplanar Crossing in Quantum Dot Cellular Automata

2020 ◽  
Vol 17 (5) ◽  
pp. 2120-2124
Author(s):  
R. Jayalakshmi ◽  
M. Senthil Kumaran ◽  
R. Amutha
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Complementary Metal Oxide Semiconductor ◽  
Basic Structure ◽  
Oxide Semiconductor ◽  
Nand Gate ◽  
Quantum Dot Cellular Automata ◽  
Wire Crossing ◽  
Majority Voter ◽  
Low Power Dissipation

The limitations of the existing Complementary Metal Oxide Semiconductor are leading the momentum to various new approaches like Quantum-dot Cellular Automata (QCA). QCA offers low power dissipation, less area and high switching speeds. The Majority Voter is the basic structure that votes out on the majority of the inputs to implement a Boolean Function. The QCA architectures are created by using majority gates with inverters or by using universal gates like AND–OR-Inverter and NAND–NOR-Inverter gate. This paper proposes a quantum-dot cellular automata 2 to 4 decoder using Universal Farooq-Nikesh-Zaid gate, which utilizes the NAND gate logic to implement the functionality. The design offers 33% reduction in the cell count, reduction in the area with Six Clock Phases in simple co planar wire crossing. The proposed design is validated using the QCA Designer tool.

Design of a New Multiplexer Structure Based on a New Fault-Tolerant Majority Gate in Quantum-Dot Cellular Automata

2021 ◽  
Author(s):  
Yaser Rahmani ◽  
Saeed Rasouli Heikalabad ◽  
Mohammad Mosleh
Keyword(s):  
Fault Tolerance ◽  
Cellular Automata ◽  
Quantum Dot ◽  
High Performance ◽  
Fault Tolerant ◽  
Cmos Technology ◽  
Good Alternative ◽  
Majority Gate ◽  
Power Efficient ◽  
Quantum Dot Cellular Automata

Abstract Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.

Quantum-Dot Cellular Automata in Designing the Arithmetic and Logic Unit: Systematic Literature Review, Classification and Current Trends

2018 ◽  
Vol 27 (10) ◽  
pp. 1830005 ◽  
Author(s):  
Mahya Rahimpour Gadim ◽  
Nima Jafari Navimipour
Keyword(s):  
Cellular Automata ◽  
Literature Review ◽  
Quantum Dot ◽  
Systematic Literature Review ◽  
Selection Process ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Future Research ◽  
Quantum Dot Cellular Automata ◽  
Logic Unit

Quantum-dot Cellular Automata (QCA) presents a new model at Nano-scale for possible substitution of conventional Complementary Metal–Oxide–Semiconductor (CMOS) technology. On the other hand, an Arithmetic Logic Unit (ALU) is a digital electronic circuit which performs arithmetic and bitwise logical operations on integer binary numbers. Therefore, QCA-based ALU is an important part of the processor in order to develop a full capability processor. Although the QCA has become very important, there is not any comprehensive and systematic work on studying and analyzing its important techniques in the field of ALU design. This paper provides the comprehensive, systematic and detailed study and survey of the state-of-the-art techniques and mechanisms in the field of QCA-based ALU designing. There are three categories in which QCA plays a role: ALU, logic unit (LU) and arithmetic unit (AU). Each category presents the important studies. In addition, this paper reviews the major developments in these three categories and it plans the new challenges. Furthermore, it provides the identification of open issues and guidelines for future research. Also, a Systematic Literature Review (SLR) on QCA-based ALU, LU and AU is discussed in this paper. We identified 1,960 papers, which are reduced to 26 primary studies through our paper selection process. According to the obtained results from 2001 to 2015, the number of published articles are very high in 2014 and low in 2005 and 2009. This survey paper also provides a discussion of considered mechanisms in terms of ALU, LU and AU attribute as well as directions for future research.

Projected Performance of Sub-10 nm GaN-based Double Gate MOSFETs

2017 ◽  
Vol 2 (2) ◽  
pp. 15-19 ◽  
Author(s):  
Md. Saud Al Faisal ◽  
Md. Rokib Hasan ◽  
Marwan Hossain ◽  
Mohammad Saiful Islam
Keyword(s):  
High Speed ◽  
Field Effect Transistors ◽  
Cmos Technology ◽  
Channel Length ◽  
Capacitive Coupling ◽  
Oxide Semiconductor ◽  
Double Gate ◽  
Short Channel ◽  
Channel Effects ◽  
Silvaco Atlas

GaN-based double gate metal-oxide semiconductor field-effect transistors (DG-MOSFETs) in sub-10 nm regime have been designed for the next generation logic applications. To rigorously evaluate the device performance, non-equilibrium Green’s function formalism are performed using SILVACO ATLAS. The device is turn on at gate voltage, VGS =1 V while it is going to off at VGS = 0 V. The ON-state and OFF-state drain currents are found as 12 mA/μm and ~10-8 A/μm, respectively at the drain voltage, VDS = 0.75 V. The sub-threshold slope (SS) and drain induced barrier lowering (DIBL) are ~69 mV/decade and ~43 mV/V, which are very compatible with the CMOS technology. To improve the figure of merits of the proposed device, source to gate (S-G) and gate to drain (G-D) distances are varied which is mentioned as underlap. The lengths are maintained equal for both sides of the gate. The SS and DIBL are decreased with increasing the underlap length (LUN). Though the source to drain resistance is increased for enhancing the channel length, the underlap architectures exhibit better performance due to reduced capacitive coupling between the contacts (S-G and G-D) which minimize the short channel effects. Therefore, the proposed GaN-based DG-MOSFETs as one of the excellent promising candidates to substitute currently used MOSFETs for future high speed applications.

Analysis and Simulation of a Low-Leakage Analog Single Gate and FinFET Circuits

2014 ◽  
Vol 13 (02) ◽  
pp. 1450012 ◽  
Author(s):  
Manorama Chauhan ◽  
Ravindra Singh Kushwah ◽  
Pavan Shrivastava ◽  
Shyam Akashe
Keyword(s):  
Integrated Circuits ◽  
Metal Oxide ◽  
Low Power ◽  
High Performance ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Short Channel ◽  
State Dependency ◽  
Low Leakage

In the world of Integrated Circuits, complementary metal–oxide–semiconductor (CMOS) has lost its ability during scaling beyond 50 nm. Scaling causes severe short channel effects (SCEs) which are difficult to suppress. FinFET devices undertake to replace usual Metal Oxide Semiconductor Field Effect Transistor (MOSFETs) because of their better ability in controlling leakage and diminishing SCEs while delivering a strong drive current. In this paper, we present a relative examination of FinFET with the double gate MOSFET (DGMOSFET) and conventional bulk Si single gate MOSFET (SGMOSFET) by using Cadence Virtuoso simulation tool. Physics-based numerical two-dimensional simulation results for FinFET device, circuit power is presented, and classifying that FinFET technology is an ideal applicant for low power applications. Exclusive FinFET device features resulting from gate–gate coupling are conversed and efficiently exploited for optimal low leakage device design. Design trade-off for FinFET power and performance are suggested for low power and high performance applications. Whole power consumptions of static and dynamic circuits and latches for FinFET device, believing state dependency, show that leakage currents for FinFET circuits are reduced by a factor of over ~ 10X, compared to DGMOSFET and ~ 20X compared with SGMOSFET.

Sign in / Sign up

Export Citation Format

Share Document