Design of quantum dot cellular automata based fault tolerant convolution encoders for secure nanocomputing

The issues faced by Complementary metal oxide semi-conductor (CMOS) technology in the nanoregime have led to the research of other possible technologies which can operate with same functionalities however, with higher speed and lower power dissipation. One such technology is Quantum-dot Cellular Automata (QCA). At present, logic circuit designs using QCA have been comprehensively researched and one such application area being investigated is data transmission. Various data transfer techniques for reliable data transfer are available and among them convolution coding is being widely used in mobile, radio and satellite communications. Considering the evolution towards nano communication networks, in this paper an ultra-proficient designs of 1/2 rate and 1/3 rate convolution encoders based on a cost-efficient and fault tolerant XOR gate design have been proposed for application in nano communication networks. Based on the performance analysis, it is observed that the proposed designs are efficient in respect to cell count, area, delay and circuit cost and achieves performance improvement up to 40.21% for 1/2 encoder and 31.81% for 1/3 encoder compared to the best design in the literature. In addition to this, the energy dissipation analysis of the proposed designs is also presented. The proposed designs can thus be efficiently utilized in various nanocommunication applications requiring minimal area and ultra-low power consumption.

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Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

Nanoscience &Nanotechnology-Asia ◽

10.2174/2210681209666190412142207 ◽

2020 ◽

Vol 10 (4) ◽

pp. 534-547

Author(s):

Chiradeep Mukherjee ◽

Saradindu Panda ◽

Asish K. Mukhopadhyay ◽

Bansibadan Maji

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Power Dissipation ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Digital Data ◽

Design Parameters ◽

Flip Flop ◽

Quantum Dot Cellular Automata ◽

Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

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Design and Analysis of Fault-Tolerant 1:2 Demultiplexer Using Quantum-Dot Cellular Automata Nano-Technology

Electronics ◽

10.3390/electronics10212565 ◽

2021 ◽

Vol 10 (21) ◽

pp. 2565

Author(s):

Saeid Seyedi ◽

Nima Jafari Navimipour ◽

Akira Otsuki

Keyword(s):

Fault Tolerance ◽

Cellular Automata ◽

Quantum Dot ◽

Fault Tolerant ◽

Nano Technology ◽

Ultra Low Power ◽

Quantum Dot Cellular Automata ◽

Whole Process ◽

Dislocation Cells ◽

Rapid Switching

Quantum-dot Cellular Automata (QCA) is an innovative paradigm bringing hopeful applications in the perceptually novel computing layout in quantum electronics. The circuits manufactured by QCA technology can provide a notable decrease in size, rapid-switching velocity, and ultra-low power utilization. The demultiplexer is a beneficial component to optimize the whole process in any logical design, and therefore is very important in QCA. Moreover, fault-tolerant circuits can improve the reliability of digital circuits by redundancy. Hence, the present investigation illustrates a novel QCA-based fault-tolerant 1:2 demultiplexer construct that employs a two-input AND gate and inverter. The functionality of the suggested layout was executed and evaluated with the utilization of the QCADesigner 2.0.3 simulator. This paper utilizes cell redundancy on the wire, inverter, and AND gates for designing a fault-tolerant demultiplexer. Four components (i.e., missing cells, dislocation cells, extra cells, and misalignment) were analyzed by the QCADesigner simulator. The simulation results demonstrated that our proposed QCA-based fault-tolerant 1:2 demultiplexer acted more efficiently than prior constructs regarding delay and fault tolerance. The proposed fault-tolerant 1:2 demultiplexer could attain high fault-tolerance when single missing cell or extra cell faults exist in the QCA layout.

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Design of a fault-tolerant reversible control unit in molecular quantum-dot cellular automata

International Journal of Quantum Information ◽

10.1142/s0219749918500107 ◽

2018 ◽

Vol 16 (01) ◽

pp. 1850010 ◽

Cited By ~ 1

Author(s):

Golnaz Bahadori ◽

Monireh Houshmand ◽

Mariam Zomorodi-Moghadam

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Fault Tolerant ◽

Control Unit ◽

Clock Frequency ◽

Ultra Low Power ◽

Quantum Dot Cellular Automata ◽

Reversible Computing ◽

Previous Design ◽

Small Feature

Quantum-dot cellular automata (QCA) is a promising emerging nanotechnology that has been attracting considerable attention due to its small feature size, ultra-low power consuming, and high clock frequency. Therefore, there have been many efforts to design computational units based on this technology. Despite these advantages of the QCA-based nanotechnologies, their implementation is susceptible to a high error rate. On the other hand, using the reversible computing leads to zero bit erasures and no energy dissipation. As the reversible computation does not lose information, the fault detection happens with a high probability. In this paper, first we propose a fault-tolerant control unit using reversible gates which improves on the previous design. The proposed design is then synthesized to the QCA technology and is simulated by the QCADesigner tool. Evaluation results indicate the performance of the proposed approach.

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Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

Applied Sciences ◽

10.3390/app112412157 ◽

2021 ◽

Vol 11 (24) ◽

pp. 12157

Author(s):

Mohsen Vahabi ◽

Pavel Lyakhov ◽

Ali Newaz Bahar ◽

Khan A. Wahid

Keyword(s):

Cellular Automata ◽

Quantum Dot ◽

Logic Gate ◽

Logic Gates ◽

Full Adder ◽

Cmos Technology ◽

Ultra Low Power ◽

Xor Gate ◽

Design Complexity ◽

Quantum Dot Cellular Automata

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

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Design & Analysis of Novel Non-Reversible & Reversible Parity Generator & Detector in Quantum Cellular Automata using Feynman Gate

Micro and Nanosystems ◽

10.2174/1876402913666210726170207 ◽

2021 ◽

Vol 13 ◽

Author(s):

Neeraj Tripathi ◽

Mohammad Mudakir Fazili ◽

Rahil Jahangir

Keyword(s):

Energy Dissipation ◽

Cellular Automata ◽

Quantum Dot ◽

Low Power ◽

Fault Tolerant ◽

Design Parameters ◽

Logic Function ◽

Ultra Low Power ◽

Quantum Dot Cellular Automata ◽

Parity Generator

Aim: A novel design for non-reversible as well as reversible parity generator and detector in Quantum-dot Cellular Automata (QCA) technology is presented in this research article. Parity generator and detector circuits are reliable error-checking components of a nano-communication system. Objective: The main focus of this research is to design an ultra-low-power fault-tolerant reversible gate implementation of the parity logic function in QCA. An efficient QCA design layout with minimal area, less latency and the least energy dissipation is desired. Methods: The proposed designs are developed using Quantum-dot Cellular Automata (QCA) technology. The circuits are optimized using majority gate reduction and clock zone reduction techniques. Also, the cell-cell interaction technique is employed to further optimize the QCA circuit. To increase the fault tolerance and for ultra-low power operation, reversible QCA circuits are designed using cascaded Feynman gates. Results and Conclusion: The efficiency of the parity generator and detector is calculated to be more than 25% compared to existing QCA layouts. It is demonstrated in this paper that the proposed circuits perform exceptionally well on every design parameter. The design parameters under consideration are cell count, cell area, complexity, crossover count, latency and energy dissipation. Using reversible logic, a fault-tolerant and defect-sensitive circuit is developed for parity generation and detection.

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Design of a New Multiplexer Structure Based on a New Fault-Tolerant Majority Gate in Quantum-Dot Cellular Automata

10.21203/rs.3.rs-355476/v1 ◽

2021 ◽

Author(s):

Yaser Rahmani ◽

Saeed Rasouli Heikalabad ◽

Mohammad Mosleh

Keyword(s):

Fault Tolerance ◽

Cellular Automata ◽

Quantum Dot ◽

High Performance ◽

Fault Tolerant ◽

Cmos Technology ◽

Good Alternative ◽

Majority Gate ◽

Power Efficient ◽

Quantum Dot Cellular Automata

Abstract Quantum-dot Cellular Automata (QCA) technology is believed to be a good alternative to CMOS technology. This nanoscale technology can provide a platform for design and implementation of high performance and power efficient logic circuits. However, the fabrication of QCA circuits is susceptible to faults appearing in this form of missing cells, additional cells, rotated cells, and displaced cells. Over the years, several solutions have been proposed to address these problems. This paper presents a new solution for improving the fault tolerance of three input majority gate. The proposed majority gate is then used to design 2-1 multiplexer and 4-1 multiplexer. The proposed designs are implemented in QCA Designer. Simulation results demonstrate significant improvements in terms of fault tolerance and area requirement.

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