scholarly journals EFFICIENT FLOATING POINT FAST FOURIER TRANSFORM BUTTERFLY ARCHITECTURE USING BINARY SIGNED DIGIT MULTIPLIER AND ADDERS

Author(s):  
Shivani Acharya ◽  
Augusta Sophy Beulet

Fast Fourier transform (FFT) is one of the most important tools in digital signal processing as well as communication system because transforming time domain to S-plane is very convenient using FFT. As FFT uses various techniques to convert a signal from time domain to S-domain and inverse, out of which butterfly technique is the one on which paper is focused on. Butterfly technique uses additions and multiplications of operands to get the required output. Floating point (FP) is used as operands due to their flexibility. As the computations involving FP has less speed, we have used binary signed digit (BSD). BSD will take the less time for addition and subtraction. Three bit BSD adder and FP adder together will make a fused dot product add (FDPA) unit. In FDPA, unit addition and subtraction will be one group and multiplication will be one group and then their respective results will be fused. Modified booth encoding and decoding algorithm are used here to make the complex multiplication with ease. 

2021 ◽  
Vol 10 (1) ◽  
pp. 59
Author(s):  
Made Sri Ayu Apsari ◽  
I Made Widiartha

Everyone has a different kind of voice. Based on gender, voice type is divided into six parts, namely soprano, mezzo soprano, and alto for women; and tenor, baritone, and bass in men. Each type of sound has a different range and with different frequencies. This study classified the type of voice in women using the Fast Fourier Transform (FFT) method by recording the voices of each user which would then be processed using the FFT method to obtain the appropriate sound range. This research got results with an accuracy of up to 80%.The results obtained from this study are quite appropriate and it is proven that the FFT method can be used in digital signal processing.


In gift scenario each method has to be compelled to be quick, adept and simple. Fast Fourier transform (FFT) may be a competent algorithmic program to calculate the N purpose Discrete Fourier transform (DFT).It has huge applications in communication systems, signal processing and image processing and instrumentation. However the accomplishment of FFT needs immense range of complicated multiplications, therefore to create this method quick and simple. It’s necessary for a number to be quick and power adept. To influence this problem the mixture of Urdhva Tiryagbhyam associate degreed Karatsuba algorithmic program offers is an adept technique of multiplication [1]. Vedic arithmetic is that the aboriginal system of arithmetic that includes a distinctive technique of calculation supported sixteen Sutras. Using these techniques within the calculation algorithms of the coprocessor can reduce the complexness, execution time, area, power etc. The distinctiveness during this project is Fast Fourier Transform (FFT) style methodology exploitation mixture of Urdhva Tiryagbhyam and Karatsuba algorithmic program based mostly floating point number. By combining these two approaches projected style methodology is time-area-power adept [1] [2]. The code writing is completed in verilog and also the FPGA synthesis on virtex 5 is completed using Xilinx ISE 14.5.


2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.


Fast Fourier Transform is an advanced algorithm for computing Discrete Fourier Transform efficiently. Although the results available from the operation of Discrete Fourier Transform (DFT) and Fast Fourier Transform (FFT) are same, but exploiting the periodicity and symmetry property of phase factor Fast Fourier Transform computes the Discrete Fourier Transform using reduced number of multiplication and addition operations. The basic structure used in the operations of Fast Fourier Transform is the Butterfly structure. For the implementation of Fast Fourier Transform the two methods are used such as decimation in time (DIT) and decimation in frequency (DIF). Both the methods give same result but for decimation in time of Fast Fourier Transform bit reversed inputs are applied and for decimation in frequency of Fast Fourier Transform normal order inputs are applied, and the result is reversed again. In this paper, operations for DFT and FFT have been discussed and shown with examples. It is found that generalized formula for FFT have been described same in the books, but the expressions in the intermediate computations for the first decimation and second decimation are different in the various books of Digital Signal Processing. The expressions in the intermediate computation of FFT described in different books are broadly compared in this paper


2016 ◽  
Vol 22 (4) ◽  
pp. 81-89
Author(s):  
Snežana Gavrilović ◽  
Nebojša Denić ◽  
Jelena Erić-Obućina ◽  
Goran Miodragović

Electronics ◽  
2021 ◽  
Vol 10 (9) ◽  
pp. 1117
Author(s):  
Bin Li ◽  
Zhikang Jiang ◽  
Jie Chen

Computing the sparse fast Fourier transform (sFFT) has emerged as a critical topic for a long time because of its high efficiency and wide practicability. More than twenty different sFFT algorithms compute discrete Fourier transform (DFT) by their unique methods so far. In order to use them properly, the urgent topic of great concern is how to analyze and evaluate the performance of these algorithms in theory and practice. This paper mainly discusses the technology and performance of sFFT algorithms using the aliasing filter. In the first part, the paper introduces the three frameworks: the one-shot framework based on the compressed sensing (CS) solver, the peeling framework based on the bipartite graph and the iterative framework based on the binary tree search. Then, we obtain the conclusion of the performance of six corresponding algorithms: the sFFT-DT1.0, sFFT-DT2.0, sFFT-DT3.0, FFAST, R-FFAST, and DSFFT algorithms in theory. In the second part, we make two categories of experiments for computing the signals of different SNRs, different lengths, and different sparsities by a standard testing platform and record the run time, the percentage of the signal sampled, and the L0, L1, and L2 errors both in the exactly sparse case and the general sparse case. The results of these performance analyses are our guide to optimize these algorithms and use them selectively.


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