scholarly journals Design and Implementation of Floating-Point Addition and Floating-Point Multiplication

Author(s):  
Nagireddy Kavya

Abstract: In this paper, we present the design and implementation of Floating point addition and Floating point Multiplication. There are many multipliers in existence in which Floating point Multiplication and Floating point addition offers a high precision and more accuracy for the data representation of the image. This project is designed and simulated on Xilinx ISE 14.7 version software using verilog. Simulation results show area reduction and delay reduction as compared to the conventional method. Keywords: FIR Filter, Floating point Addition, Floating point Multiplication, Carry Look Ahead Adder

2015 ◽  
Vol 2015 ◽  
pp. 1-10 ◽  
Author(s):  
Anitha Juliette Albert ◽  
Seshasayanan Ramachandran

Floating point multiplication is a critical part in high dynamic range and computational intensive digital signal processing applications which require high precision and low power. This paper presents the design of an IEEE 754 single precision floating point multiplier using asynchronous NULL convention logic paradigm. Rounding has not been implemented to suit high precision applications. The novelty of the research is that it is the first ever NULL convention logic multiplier, designed to perform floating point multiplication. The proposed multiplier offers substantial decrease in power consumption when compared with its synchronous version. Performance attributes of the NULL convention logic floating point multiplier, obtained from Xilinx simulation and Cadence, are compared with its equivalent synchronous implementation.


Author(s):  
Mutyala Sri Anantha Lakshmi

Abstract: In this paper, we present the design and implementation of the Radix 8 Booth Encoding Multiplier. There are many multipliers in existence in which Radix 8 Booth Encoding Multiplier offers a decrease in area and provides high speed due to its diminution in the number of partial products. This project is designed and simulated on Xilinx ISE 14.7 version software using VHDL (Very High Speed Integrated Circuit Hardware Description Language). Simulation results show area reduction by 33.4% and delay reduction by 45.9% as compared to the conventional method. Keywords: Booth Multiplier, Radix 8, Partial Product


2019 ◽  
Vol 8 (2S3) ◽  
pp. 1064-1067

Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.Multiplication of floating point(FP) numbers is greatly significant in many DSP applications. The performance of the DSP’s is substantially decided by the speed of the multipliers used. This paper proposes the design and implementation of IEEE 754 standard single precision FP multiplier using Verilog, synthesized and simulated in Xilinx ISE10.1. Urdhva Triyagbhyam Sutra of Vedic mathematics is used for the unsigned mantissa calculation. The design implements floating point multiplication with sign bit and exponent calculations. The proposed design is achieved high speed with minimum delay of 3.997ns.


1996 ◽  
Vol 143 (5) ◽  
pp. 325
Author(s):  
A. Beaumont-Smith ◽  
W. Marwood ◽  
C.C. Lim ◽  
K. Eshraghian

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