Novel Integrated Low Capacitance Transient Voltage Suppressor Array with Capacitance Equalization Technique for System-Level EOS/ESD Protection

Author(s):  
Zhao Qi ◽  
Ming Qiao ◽  
Fei Zhao ◽  
Zhaoji Li ◽  
Bo Zhang
2010 ◽  
Vol 49 (4) ◽  
pp. 04DP13 ◽  
Author(s):  
Sheng-Huei Dai ◽  
Jeng-Jie Peng ◽  
Chia-Cheng Chen ◽  
Chrong-Jung Lin ◽  
Ya-Chin King

2009 ◽  
Author(s):  
C. C. Chen ◽  
S. H. Dai ◽  
J. J. Peng ◽  
C. J. Lin ◽  
Y. C. King

2021 ◽  
Vol 35 (04) ◽  
pp. 2150052
Author(s):  
yibo Jiang ◽  
Hui Bi ◽  
Zhihao Xu ◽  
Wei Zhao ◽  
Yuanyuan Zhang ◽  
...  

The electronic circuits fabricated in a variety of technologies for different applications are all vulnerable to the electrostatic discharge (ESD) event. In this paper, polysilicon devices are investigated as ESD protection because of the noticeable advantages such as compatibility with several technologies, low parasitical capacitance, and little noise coupling. By forming the p-i-n diode in the polysilicon layer and stacking them together, the single polysilicon diode (SPD) and cascaded polysilicon diode (CasPD) are implemented in the 0.35 [Formula: see text] high voltage diffusion process. Through DC IV/CV, transmission line pulse (TLP), and zipping test, the CasPD presents as ESD protection for an S-band RF power amplifier, with high process-compatibility, modulable voltage, low leakage current and parasitic capacitance.


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