Capacitive Measurements of SiO2 Films of Different Thicknesses Using a MOSFET-Based SPM Probe

We utilized scanning probe microscopy (SPM) based on a metal-oxide-silicon field-effect transistor (MOSFET) to image interdigitated electrodes covered with oxide films that were several hundred nanometers in thickness. The signal varied depending on the thickness of the silicon dioxide film covering the electrodes. We deposited a 400- or 500-nm-thick silicon dioxide film on each sample electrode. Thick oxide films are difficult to analyze using conventional probes because of their low capacitance. In addition, we evaluated linearity and performed frequency response measurements; the measured frequency response reflected the electrical characteristics of the system, including the MOSFET, conductive tip, and local sample area. Our technique facilitated analysis of the passivation layers of integrated circuits, especially those of the back-end-of-line (BEOL) process, and can be used for subsurface imaging of various dielectric layers.

Polysilicon devices as a highly compatible ESD protection with modulable voltage and low capacitance

The electronic circuits fabricated in a variety of technologies for different applications are all vulnerable to the electrostatic discharge (ESD) event. In this paper, polysilicon devices are investigated as ESD protection because of the noticeable advantages such as compatibility with several technologies, low parasitical capacitance, and little noise coupling. By forming the p-i-n diode in the polysilicon layer and stacking them together, the single polysilicon diode (SPD) and cascaded polysilicon diode (CasPD) are implemented in the 0.35 [Formula: see text] high voltage diffusion process. Through DC IV/CV, transmission line pulse (TLP), and zipping test, the CasPD presents as ESD protection for an S-band RF power amplifier, with high process-compatibility, modulable voltage, low leakage current and parasitic capacitance.

Sequential Switching Shunt Regulator Parallel Power Processing Control for High Capacitance Solar Arrays

This paper presents a new control strategy for reducing the switching losses produced by the use of high parasitic capacitance solar arrays in the sequential switching shunt regulator. Instead of dividing the solar array into equal sections, the proposed strategy is based on two different sections types, low-capacitance and high-capacitance ones. In order to reduce the switching losses and to maintain the original closed-loop response, a novel parallel power processing control strategy is implemented. With this new technique the low-capacitance sections are the only ones that switch at high frequency to regulate the bus while the high-capacitance sections are only connected or disconnected under high load power changes. In addition, the control closed loop delay associated to the time needed to charge the parasitic capacitance has been modelled and a controller modification is proposed to reduce AC performance degradation.