Digital-Filter-Based Compensation of Case Effect in Sound-Level Meters

2010 ◽  
Vol 56 (3) ◽  
pp. 263-266
Author(s):  
Andrzej Miękina ◽  
Andrzej Podgórski
Keyword(s):  
Digital Filter ◽  
Digital Signal Processor ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Sound Level ◽  
Remez Algorithm ◽  
The Family ◽  
On Chip ◽  
Level Meter ◽  
Case Effect

Digital-Filter-Based Compensation of Case Effect in Sound-Level Meters The methodology for the design of a digital filter, which should compensate the effect of reflections and diffraction from the sound-level meter's casing (the so-called case effect), is presented. The coefficients of the family of the finite impulse response (FIR) filters, which were selected to fulfill the requirements of the compensation, were obtained in the MATLAB environment using the Remez algorithm. The frequency response of the selected designed filter are given. The chosen FIR filter was implemented in an on-chip Enhanced Filter Coprocessor of a fixed point 24-bit digital signal processor of a sound-level meter.

scholarly journals Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning

2021 ◽  
Vol 27 (3) ◽  
pp. 57-70
Author(s):  
Damjan M. Rakanovic ◽  
Vuk Vranjkovic ◽  
Rastislav J. R. Struharik
Keyword(s):  
Digital Signal Processor ◽  
State Of The Art ◽  
Digital Signal ◽  
Pruning Algorithm ◽  
Kernel Clustering ◽  
Field Programmable ◽  
Comparable Performance ◽  
On Chip ◽  
Resource Characteristics ◽  
Resource Aware

Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelerator requires about 170 Look-up tables (LUTs) per Digital Signal Processor (DSP) block. This number is close to the average LUT/DPS ratio for various FPGA families, enabling balanced resource utilization when implementing Argus. Benchmarks conducted using Xilinx Zynq Ultrascale + Multi-Processor System-on-Chip (MPSoC) indicate that Argus is achieving up to 25 times higher frames per second than NullHop, 2 and 2.5 times higher than NEURAghe and Snowflake, respectively, and 2 times higher than NVDLA. Argus shows comparable performance to MIT’s Eyeriss v2 and Caffeine, requiring up to 3 times less memory bandwidth and utilizing 4 times fewer DSP blocks, respectively. Besides the absolute performance, Argus has at least 1.3 and 2 times better GOP/s/DSP and GOP/s/Block-RAM (BRAM) ratios, while being competitive in terms of GOP/s/LUT, compared to some of the state-of-the-art solutions.

Digital Signal Processing Approach of Dithered RLG Based on IFIR Digital Filter

2014 ◽  
Vol 989-994 ◽  
pp. 4195-4199
Author(s):  
Kui Zhang ◽  
Gong Liu Yang ◽  
Wei Zhen Zheng ◽  
Ren Dong Ma
Keyword(s):  
Impulse Response ◽  
Digital Filter ◽  
Group Delay ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Noise Attenuation ◽  
Computation Complexity ◽  
Ring Laser Gyroscope ◽  
Laser Gyroscope ◽  
Filter Approach

An interpolated finite impulse response (IFIR) digital filter approach was purposed to improve the demerits of traditional finite impulse response (FIR) digital filter in the case of noise attenuation for dithered Ring Laser Gyroscope (RLG). Concentrated on the time delay and computation complexity, a comparison of FIR and IIR digital filter was illustrated. By optimizing the stretch factor L, an IFIR digital filter was designed to reach the requirements of a typical RLG. The static experiment results show that the impulse number is decreased from 250 to below 0.15, attenuation of the dither noise is nearly 100 dB and group delay remains the same level by 11.25ms.

scholarly journals Real Time Digital Filter for a Front-End Electronics in Dark Matter and Neutrino Measurements

2020 ◽  
Author(s):  
Alejandro D. Martinez R. ◽  
On behalf of DarkSide Collaboration
Keyword(s):  
Dark Matter ◽  
Real Time ◽  
Digital Filter ◽  
Signal To Noise Ratio ◽  
Digital Signal ◽  
Pulse Shaper ◽  
Signal Processing Algorithm ◽  
Front End ◽  
Photo Detection ◽  
On Chip

This paper presents real-time digital filter algorithms to be applied within dark matter and neutrino measurements. The digital signal processing algorithm implements a trapezoidal pulse-shaper programmed on FPGA at 125 MHz. The real-time filter algorithm enhances the SNR of a digitized signal from a photo detection module (SiPM, cryogenic front-end electronics & 14-bits ADC). The trapezoidal filter upgrades the signal to noise ratio (SNR) from 10.4 to 15.4 with a total increment of 50%. The total on-chip power is 0.198 W.

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