scholarly journals A Low Area, Low Power 8-bit AES-CCM Authenticated Encryption Core in 180nm CMOS Process

2018 ◽  
Vol 34 (1) ◽  
Author(s):  
Dao Van Lan ◽  
Nguyen Anh Thai ◽  
Hoang Van Phuc
Keyword(s):  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Ieee 802.15.6 ◽  
Authenticated Encryption ◽  
Low Area ◽  
High Resource ◽  
Operation Speed ◽  
Very High ◽  
Iterative Structure

This paper presents a low area, low power AES-CCM authenticated encryption IP core with silicon demonstration in 180nm standard CMOS process. The proposed AES-CCM core combines a low area 8-bit single S-box AES encryption core, improved iterative structure and other optimized circuits. The implementation results show that the proposed AES-CCM core achieves very high resource efficiency with 6.5 kgates GE and the low power consumption of 11.6 µW/MHz while meeting the requirement of the operation speed for many applications including IEEE 802.15.6 WBANs. The detail implementation and optimization results are also presented and discussed.

A 260-μW Down-Conversion Demodulator for MICS-Band Receiver

2016 ◽  
Vol 26 (02) ◽  
pp. 1750027 ◽  
Author(s):  
Chia-Hung Chang ◽  
Cihun-Siyong Alex Gong ◽  
Jian-Chiun Liou ◽  
Yu-Lin Tsou ◽  
Feng-Lin Shiu ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Communication Services ◽  
Ultra Low Power ◽  
Resistive Feedback ◽  
Mics Band ◽  
Down Conversion ◽  
Implant Communication

This paper showcases a low-power demodulator for medical implant communication services (MICS) applications. Complementary shunt resistive feedback, current reuse configuration, and sub-threshold LO driving techniques are proposed to achieve ultra-low power consumption. The chip has been implemented in standard CMOS process and consumes only 260-[Formula: see text]W.

A NOVEL SWITCHED-CURRENT SUCCESSIVE APPROXIMATION ADC

2011 ◽  
Vol 20 (01) ◽  
pp. 15-27 ◽  
Author(s):  
XIAN TANG ◽  
KONG PANG PUN
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Successive Approximation ◽  
High Speed ◽  
High Accuracy ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Power Efficient ◽  
Successive Approximation Adc ◽  
Switched Current

A novel switched-current successive approximation ADC is presented in this paper with high speed and low power consumption. The proposed ADC contains a new high-accuracy and power-efficient switched-current S/H circuit and a speed-improved current comparator. Designed and simulated in a 0.18-μm CMOS process, this 8-bit ADC achieves 46.23 dB SNDR at 1.23 MS/s consuming 73.19 μW under 1.2 V voltage supply, resulting in an ENOB of 7.38-bit and an FOM of 0.357 pJ/Conv.-step.

scholarly journals High Speed and Low Power Consumption by Exploitation using Novel XOR and XNOR Gates

2019 ◽  
Vol 8 (12S) ◽  
pp. 1182-1186
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
High Speed ◽  
Short Circuit ◽  
Full Adder ◽  
Low Power Consumption ◽  
Cmos Process ◽  
Input Noise ◽  
Threshold Voltages ◽  
Output Capacitance

The present paper proposes a high speed and low power consumption by travelling novel XOR and XNOR gates. The present circuit consist optimized power intakeas well asdelay due to smallamount produced capacitance and power dissipation for low short circuit. Here we utilize 6 new hybrid 1 bit full adder circuitthat produces to and fro XOR/XNOR gates. Here the present circuit has its own advantages like rapidity, power consumption and delay in power product, dynamic capability and so on. Here we proposed signals like HSPICE, Cadence simulations for investigating the performance results which are based on 65-nm CMOS process technical models that indicate high speed and power against FA signals. So here we propose a novel new transistor sizing method that optimizes the PDP circuits. The present circuit investigates on various supply terms of variations like threshold voltages, size of transistors, input noise and output capacitance by utilizing numerical computation particle swam optimization algorithm for achieving desired value in optimum PDP with few iterations

Design of Voltage-Mode MAX-MIN Circuits with Low Area and Low Power Consumption

2009 ◽  
Vol E92-A (12) ◽  
pp. 3044-3051 ◽  
Author(s):  
Mohammad SOLEIMANI ◽  
Abdollah KHOEI ◽  
Khayrollah HADIDI ◽  
Vahid Fagih DINAVARI
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Consumption ◽  
Voltage Mode ◽  
Low Area

scholarly journals Low Power CMOS-Based Hall Sensor with Simple Structure Using Double-Sampling Delta-Sigma ADC

Sensors ◽  
2020 ◽  
Vol 20 (18) ◽  
pp. 5285
Author(s):  
Juyong Lee ◽  
Younggyun Oh ◽  
Sein Oh ◽  
Hyungil Chae
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Simple Structure ◽  
Hall Sensor ◽  
Total Power ◽  
Low Power Consumption ◽  
Double Sampling ◽  
Cmos Process ◽  
Delta Sigma ◽  
Total Power Consumption

A CMOS (Complementary metal-oxide-semiconductor) Hall sensor with low power consumption and simple structure is introduced. The tiny magnetic signal from Hall device could be detected by a high-resolution delta-sigma ADC in presence of offset and flickering noise. Also, the offset as well as the flickering noise are effectively suppressed by the current spinning technique combined with double sampling switches of the ADC. The double sampling scheme of the ADC reduces the operating frequency and helps to reduce the power consumption. The prototype Hall sensor is fabricated in a 0.18-µm CMOS process, and the measurement shows detection range of ±150 mT and sensitivity of 110 µV/mT. The size of active area is 0.7 mm2, and the total power consumption is 4.9 mW. The proposed system is advantageous not only for low power consumption, but also for small sensor size due to its simplicity.

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