A COMBINED APPROACH TO CREATING MODELS FOR H-TYPE TRANSISTORS MADE USING 0.18 MICRON SOI TECHNOLOGY
2020 ◽
Keyword(s):
A technique has been developed for extracting the parameters of a compact H-transistor model based on BSIMSOI 4.5, taking into account parasitic capacitances, and also using the binning approach to take into account the non-standard dependence of the I–V characteristic on the geometrical dimensions of the transistor.
Keyword(s):
2019 ◽
Vol 12
(12)
◽
pp. 3254-3264
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1975 ◽
Vol 18
(11)
◽
pp. 949-963
◽
Keyword(s):