Schemes for Single Electron Transistor Based on Double Quantum Dot Islands Utilizing a Graphene Nanoscroll, Carbon Nanotube and Fullerene

The single electron transistor (SET) is a nanoscale switching device with a simple equivalent circuit. It can work very fast as it is based on the tunneling of single electrons. Its nanostructure contains a quantum dot island whose material impacts on the device operation. Carbon allotropes such as fullerene (C60), carbon nanotubes (CNTs) and graphene nanoscrolls (GNSs) can be utilized as the quantum dot island in SETs. In this study, multiple quantum dot islands such as GNS-CNT and GNS-C60 are utilized in SET devices. The currents of two counterpart devices are modeled and analyzed. The impacts of important parameters such as temperature and applied gate voltage on the current of two SETs are investigated using proposed mathematical models. Moreover, the impacts of CNT length, fullerene diameter, GNS length, and GNS spiral length and number of turns on the SET’s current are explored. Additionally, the Coulomb blockade ranges (CB) of the two SETs are compared. The results reveal that the GNS-CNT SET has a lower Coulomb blockade range and a higher current than the GNS-C60 SET. Their charge stability diagrams indicate that the GNS-CNT SET has smaller Coulomb diamond areas, zero-current regions, and zero-conductance regions than the GNS-C60 SET.

High-frequency rectifying characteristics of metallic single-electron transistor with niobium nanodots

Metallic single-electron transistors (SETs) with niobium nanodots were fabricated, and their high-frequency rectifying characteristics were evaluated. By reducing the gap size of the electrodes and film deposition area to nanometer scale, improved SET characteristics with gate control, and better frequency response of the rectifying current with gentler decrease than 1/f at high frequency were achieved. The comparison between the characteristics of micrometer- and nanometer-size devices are made, and the reason for their differences are discussed with a help of simulation based on the experimentally extracted parameters.

Parallel Comparator based voltmeter using Single Electron Tunneling Transistor

By manipulating an electron that tunnels the tunnel junction of a single electron transistor, one will be able to reach a standard output logic “1” or logic “0”. The operation of the Single Electron Transistor (SET) is depending upon the bias voltage as well as the input signal(s). By varying the input voltage levels of a SET, the output voltage levels can significantly be changed on the basis of tunneling of an electron whether tunneling happened or not. As our concentration is the measuring of an unknown voltage, we are to implement a voltmeter system to provide a digital output of 3 bits whenever an unknown input voltage is kept in touching in the input terminal. A reference/standard voltage (say 8mV) will be connected in series with eight resistances ( 8 Rs) for the purpose of making a seven threshold voltages, for 7 comparators, in an ascending order of values from ground to reference voltage for seven comparators which are used in this present work. The voltmeter implemented consists of (i) a voltage divider, (ii) a set of seven comparators, (iii) seven Exclusive-OR gates and (iv) three 4-input OR gates. The concepts of implementing “Parallel Comparator based voltmeter” is discussed in two ways (i) by classical block diagram and (ii) using Single electron transistor based circuit. The measuring of an input analog voltage will not be the same as the digital output value. A 3-bit output indicates that the input analog voltage must lie on within a particular small range of voltage. The encoder circuit which is connected to the outputs of the comparators is hard to construct whenever the three terminals output are expressed with the output variables (Wi) of the comparators. For simple and user-friendly circuit, the outputs (Wi) of the comparators are modified to Di variables so as to get the same 3-bit encoder/voltmeter output. For this purpose, 7 extra component called 2-input XORs based on SET are used. Seven such XORs are set, and the output of them are passed to three 4-input OR gates according to the required logic expressions. It is found that all the output data of the voltmeter are coherently matched with the theoretical aspects. Processing delays are found out for all circuits. Power consumptions of all of them are shown in tabular and graphical forms. All the circuit we are intending to make are provided in due places with their logic circuit or simulation set and the simulation results are provided as well. Different truth tables are given for keeping track of whether input-output relationships matches with the theoretical results. We have thought of whether the present work circuits are faster or slower than the circuits of CMOS based-circuits. The power consumed at the time of tunneling event for a circuit is measured and sensed that it exists in the range between 1×10^(-18) Joules to 22×10^(-18)Joules which is very small amount. All the combinational circuits presented in this work are of SET-based.

Conductance peaks and gaps in single-electron device with the presence of electron-electron interaction - “Nonequilibrium green function approach”

Consider a single-electron transistor (SET) with a small size quantum dot (QD), where confined energy and the Coulomb interaction control the charges adding to QD. In this paper, a theoretical analysis of the relation between source-drain voltage and gate voltage has been done to define quantum-Coulomb blocked (and unblocked) diamonds for QD that has N electrons. An analytical equation for the conductance has been derived using the non-equilibrium Green function technique (NEGFT). Further, the effect of QD size and the tunnelling rate on conductance peaks and gaps have been investigated. Finally, the effect of gate voltage on conductance peaks and gaps with respect the quantum-Coulomb blocked regions has been analysed.

Finding out square root of an integer number using Single Electron Transistor

The single-electron transistor (SET) attracts the researchers, scientists or technologists to design and construct large scale circuits for the sake of the consumption of ultra-low power and its small size. All the incidences in a SET-based circuit happen when only a single electron tunnels through the transistors under the proper applied bias voltage and a small gate voltage or multiple gate voltages. The oscillatory conduction as the function of the variable-multiple /single gate voltage is exhibited by SET. This uncommon characteristic provides the ability of executing the functions of AND, OR, XOR, Inverter and some combinational circuits like multiplexer, subtractor etc. For implementing a square root circuit, SET would be a best candidate to fulfil the requirements. The processing speed of SET based devices will be nearly close to electronic speed. Noise during processing gets ultra-low when the circuits is built with SETs. The square root circuit is presented here for sixteen bit input numbers. The input bit numbers can be increased with the increasing of the depth of the pattern very easily. And this will provide us the greater accuracy about the squared root value. Power consumption in the single electron circuit is low irrespective of bipolar junction transistor (BJT) or Complementary Metal Oxide Semiconductor (CMOS) circuits. Reducing the numbers of nodes, the power consumption is reduced.

Model of a single-electron transistor based on endohedral fullerene (Sc3N)@C80

In this work within the framework of the density functional theory and the method of nonequilibrium Green’s functions the dependences of the total energy of molecules C80-SET and (Sc3N)@C80 - SET on their total charge, the dependence of the total energy from the gate voltage and the stability diagram of the single-electron transistor have been determined. It is noted that for transition to switch to on mode (Sc3N)@C80-SET it is necessary to apply the gate voltage in the range from 0.019 ≤ VG ≤ 5.940 with the bias voltage -2.040 ≤ VSD ≤ 2.155 V. Considering that at values of bias voltage equal to –0.381 ≤ VSD ≤ 0.533 V there is no voltage on the substrate (VG = 0 V) and electric current does not flow. It is shown that the total energy at negative values of charge is higher than at positive charges and that the area of the Coulomb rhombus in fullerene with scandium nitride is 5.3 times larger than in “pure” fullerene.

Detecting Air Pollutant Molecules Using Tube-Shaped Single Electron Transistor

An air pollution detector is proposed based on a tube-shaped single-electron transistor (SET) sensor. By monitoring the flow control component of the detector, each air pollutant molecule can be placed at the center of a SET nanopore and is treated as an island of the SET device in the same framework. Electron transport in the SET was incoherent, and the performances of the SET were sensitive at the single molecule level. Employing first-principles calculations, electronic features of an air pollutant molecule within a tube-shaped SET environment were found to be independent of the molecule rotational orientations with respect to axis of symmetry, unlike the electronic features in a conventional SET environment. Charge stability diagrams of the island molecules were demonstrated to be distinct for each molecule, and thus they can serve as electronic fingerprints for detection. Using the same setup, quantification of the air pollutant can be realized at room temperature as well. The results presented herein may help provide guidance for the identification and quantification of various types of air pollutants at the molecular level by treating the molecule as the island of the SET component in the proposed detector.

Electromechanical Characteristics by a Vertical Flip of C70 Fullerene Prolate Spheroid in a Single-Electron Transistor: Hybrid Density Functional Methods

In this study, the B3LYP hybrid density functional theory was used to investigate the electromechanical characteristics of C70 fullerene with and without point charges to model the effect of the surface of the gate electrode in a C70 single-electron transistor (SET). To understand electron tunneling through C70 fullerene species in a single-C70 transistor, descriptors of geometrical atomic structures and frontier molecular orbitals were analyzed. The findings regarding the node planes of the lowest unoccupied molecular orbitals (LUMOs) of C70 and both the highest occupied molecular orbitals (HOMOs) and the LUMO of the C70 anion suggest that electron tunneling of pristine C70 prolate spheroidal fullerene could be better in the major axis orientation when facing the gate electrode than in the major (longer) axis orientation when facing the Au source and drain electrodes. In addition, we explored the effect on the geometrical atomic structure of C70 by a single-electron addition, in which the maximum change for the distance between two carbon sites of C70 is 0.02 Å.