scholarly journals Hardware Implementation for the HEVC Fractional Motion Estimation Targeting Real-Time and Low-Energy

2016 ◽  
Vol 11 (2) ◽  
pp. 106-120 ◽  
Author(s):  
Vladimir Afonso ◽  
Henrique Maich ◽  
Luan Audibert ◽  
Bruno Zatt ◽  
Marcelo Porto ◽  
...  
Keyword(s):  
Motion Estimation ◽  
High Efficiency ◽  
Hardware Design ◽  
Resource Usage ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Energy Aware ◽  
Hardware Resource ◽  
High Processing ◽  
Fractional Motion Estimation

This paper presents an energy-aware and high-throughput hardware design for the Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) standard. An extensive software evaluation was performed to guide the hardware design. The adopted strategy mainly consists in using only the four squareshaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes in the Motion Estimation (ME). This approach reduces about 59% the total encoding time and, as a penalty, it leads to an increase of only 4% in the bit rate for the same image quality. Together with this simplification, a multiplierless approach, algebraic optimizations and low-power techniques were applied to the hardware design to reduce the hardware-resource usage and the energy consumption, maintaining a high processing rate. The architecture was described in VHDL and the synthesis results for ASIC 45nm Nangate standard cells demonstrate that the developed architecture is able to process Ultra-High Definition (UHD) 2160p videos at 60 frames per second (fps), with the lowest power consumption and the lowest hardware-resource usage among the related works.

scholarly journals Energy and Rate-Aware Design for HEVC Motion Estimation Based on Pareto Efficiency

2018 ◽  
Vol 13 (1) ◽  
pp. 1-12
Author(s):  
Murilo Roschildt Perleberg ◽  
Vladimir Afonso ◽  
Ruhan Conceição ◽  
Altamiro Susin ◽  
Luciano Agostini ◽  
...  
Keyword(s):  
Motion Estimation ◽  
High Efficiency ◽  
Hardware Design ◽  
Control Unit ◽  
Pareto Efficiency ◽  
External Control ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Average Case ◽  
Test Zone

This paper presents a high-throughput energy and rate-aware hardware design for the Motion Estimation (ME) according to the High Efficiency Video Coding (HEVC) standard. The hardware design implements a modified Test Zone Search (TZS) algorithm to perform Integer Motion Estimation (IME) as well as the Fractional Motion Estimation (FME) defined by the HEVC standard. Based on evaluations with the HEVC Reference Software, a complexity-reduction strategy was adopted in the developed architecture that mainly consists of supporting only the 8x8, 16x16, 32x32, and 64x64 Prediction Unit (PU) sizes rather than using the 24 possible PU sizes. The architecture allows an external control unit selects a subset of these four PU sizes according to the energy and rate targets for a specific application. The possible operation points were determined based on Pareto Efficiency. The architecture was described in VHDL, and the synthesis results for ASIC 45nm Nangate standard cells show that the developed architecture can process at least 53 frames per second (fps) considering Ultra-High Definition (UHD) 4320p videos. When an average-case of processing is considered, the architecture is able to process 112fps at UHD 4320p resolution.

scholarly journals Motion Estimation in HEVC/H.265: Metaheuristic Approach to Improve the Efficiency

2021 ◽  
Vol 12 (1) ◽  
pp. 59
Author(s):  
Khwaja Humble Hassan ◽  
Shahzad Ahmad Butt
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
High Efficiency ◽  
Optimization Problems ◽  
Search Algorithm ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
The Social ◽  
Test Zone ◽  
Encoding Efficiency

An ever increasing use of digital video applications such as video telephony, broadcast and the storage of high and ultra-high definition videos has steered the development of video coding standards. The state of the art video coding standard is High Efficiency Video Coding (HEVC) or otherwise known as H.265. It promises to be 50 percent more efficient than the previous video coding standard H.264. Ultimately, H.265 provides significant improvement in compression at the expense of computational complexity. HEVC encoder is very complex and 50 percent of the encoding consists of Motion Estimation (ME). It uses a Test Zone (TZ) fast search algorithm for its motion estimation, which compares a block of pixels with a few selected blocks in the search region of a referenced frame. However, the encoding time is not suitable to meet the needs of real time video applications. So, there is a requirement to improve the search algorithm and to provide comparable results to TZ search to save a substantial amount of time. In our paper, we aim to study the effects of a meta-heuristic algorithm on motion estimation. One such suitable algorithm for this task is the Firefly Algorithm (FA). FA is inspired by the social behavior of fireflies and is generally used to solve optimization problems. Our results show that implementing FA for ME saves a considerable amount of time with a comparable encoding efficiency.

scholarly journals Low-Cost and High-Throughput Hardware Design for the HEVC 16x16 2-D DCT Transform

2014 ◽  
Vol 9 (1) ◽  
pp. 25-35
Author(s):  
Ruhan Conceição ◽  
José Cláudio De Souza Jr ◽  
Ricardo Jeske ◽  
Bruno Zatt ◽  
Marcelo Porto ◽  
...  
Keyword(s):  
Video Coding ◽  
High Throughput ◽  
High Efficiency ◽  
Low Cost ◽  
Hardware Design ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Real Time Processing ◽  
Dct Transform ◽  
Control Overhead

This article presents the hardware design of the 16x16 2-D DCT used in the new video coding standard, the HEVC – High Efficiency Video Coding. The transforms stage is one of the innovations proposed by HEVC, since a variable size transforms stage is available (from 4x4 to 32x32), allowing the use of transforms with larger dimensions than used in previous standards. The presented design explores the 2-D DCT separability property, using two instances of the one-dimension DCT. The architecture focuses on low hardware cost and high throughput, thus the HEVC 16-points DCT algorithm was simplified targeting a more efficient hardware implementation. Operations and hardware minimization strategies were used in order to achieve such simplifications: operation reordering, factoring, multiplications to shift-adds conversion, and sharing of common sub-expressions. The 1-D DCT architectures were designed in a fully combinational way in order to reduce control overhead. A transposition buffer is used to connect the two 1-D DCT architectures. The synthesis was directed to Stratix III FPGA and TSMC 65nm standard cells technologies. The complete 2-D DCT architecture is able to achieve real-time processing for high and ultra-high definition videos, such as Full HD, QFHD and UHD 8K. When compared with related works, the architectures designed in this work reached the highest throughput and the lowest hardware resources consumption.

scholarly journals Robust and fast selective encryption for HEVC videos

2014 ◽  
Vol 10 (4) ◽  
pp. 221 ◽  
Author(s):  
Mokhtar Ouamri ◽  
Kamel M. Faraoun
Keyword(s):  
High Efficiency ◽  
Operating Mode ◽  
Advanced Encryption Standard ◽  
Selective Encryption ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Network Applications ◽  
Encryption Schemes ◽  
Visual Degradation ◽  
Reliability And Robustness

Emerging High efficiency video coding (HEVC) is expected to be widely adopted in network applications for high definition devices and mobile terminals. Thus, construction of HEVC's encryption schemes that maintain format compliance and bit rate of encrypted bitstream becomes an active security's researches area. This paper presents a novel selective encryption technique for HEVC videos, based on enciphering the bins of selected Golomb–Rice code’s suffixes with the Advanced Encryption Standard (AES) in a CBC operating mode. The scheme preserves format compliance and size of the encrypted HEVC bitstream, and provides high visual degradation with optimized encryption space defined by selected Golomb–Rice suffixes. Experimental results show reliability and robustness of the proposed technique.

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