scholarly journals Design of Transfer-Gated CMOS Active Pixels Deploying Conventional PN-Junction Photodiodes

2020 ◽  
Vol 15 (3) ◽  
pp. 1-7
Author(s):  
Lidiane Campos Costa ◽  
Rubens A. Souza ◽  
Davies W. de Lima Monteiro ◽  
Luciana P. Salles

This paper presents a comparative study of six active pixel sensor (APS) schemes by means of simulations and experiments. The optical sensor used was a silicon photodiode with integrated electronics in a standard 0.35 µm CMOS technology. We analyzed how the transistor characteristics, such as channel resistance and leakage current, among others, can influence the APS response. Furthermore, we demonstrated how the choice of APS model affects sensor parameters such as output swing and fill factor, among others. The results presented and the understanding of the operational cycle of the CMOS transfer-gated APS aims at guiding better choices for different applications and the better transistor type in the project.

2011 ◽  
Vol 42 (11) ◽  
pp. 1269-1275 ◽  
Author(s):  
Pedro F. Leite Retes ◽  
Frank Sill Torres ◽  
Davies W. de Lima Monteiro

2008 ◽  
Vol 8 (3) ◽  
pp. 501-508 ◽  
Author(s):  
Xiaobin Yuan ◽  
Jae-Eun Park ◽  
Jing Wang ◽  
Enhai Zhao ◽  
David C. Ahlgren ◽  
...  

2014 ◽  
Vol 9 (05) ◽  
pp. C05064-C05064 ◽  
Author(s):  
A Miucci ◽  
L Gonella ◽  
T Hemperek ◽  
F Hügging ◽  
H Krüger ◽  
...  

Author(s):  
Tejaswini M. L ◽  
Aishwarya H ◽  
Akhila M ◽  
B. G. Manasa

The main aim of our work is to achieve low power, high speed design goals. The proposed hybrid adder is designed to meet the requirements of high output swing and minimum power. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of XOR-XNOR circuit. In hybrid FAs maximum power is consumed by XOR-XNOR circuit. In this paper 10T XOR-XNOR is proposed, which provide good driving capabilities and full swing output simultaneously without using any external inverter. The performance of the proposed circuit is measured by simulating it in cadence virtuoso environment using 90-nm CMOS technology. This circuit outperforms its counterparts showing power delay product is reduced than that of available XOR-XNOR modules. Four different full adder designs are proposed utilizing 10T XOR-XNOR, sum and carry modules. The proposed FAs provide improvement in terms of PDP than that of other architectures. To evaluate the performance of proposed full adder circuit, we embedded it in a 4-bit and 8-bit cascaded full adder. Among all FAs two of the proposed FAs provide the best performance for a higher number of bits.


IFAE 2006 ◽  
2007 ◽  
pp. 349-352
Author(s):  
V. Re ◽  
C. Andreoli ◽  
M. Manghisoni ◽  
E. Pozzati ◽  
L. Ratti ◽  
...  

Author(s):  
Xiaobin Yuan ◽  
Jae-Eun Park ◽  
Jing Wang ◽  
Enhai Zhao ◽  
David Ahlgren ◽  
...  

2005 ◽  
Vol 52 (3) ◽  
pp. 752-755 ◽  
Author(s):  
E.G. Villani ◽  
P.P. Allport ◽  
G. Casse ◽  
A. Evans ◽  
M. Tyndel ◽  
...  

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