scholarly journals Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium–Gallium–Zinc Oxide Thin-Film Transistors

Coatings ◽  
2021 ◽  
Vol 11 (10) ◽  
pp. 1192
Author(s):  
Dae-Hwan Kim ◽  
Hwan-Seok Jeong ◽  
Dong-Ho Lee ◽  
Kang-Hwan Bae ◽  
Sunhee Lee ◽  
...  

We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were located further away from the interface, through the Poole–Frenkel effect. Accordingly, we quantitatively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultaneously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS termination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method.

Materials ◽  
2019 ◽  
Vol 12 (6) ◽  
pp. 852 ◽  
Author(s):  
Seungbeom Choi ◽  
Kyung-Tae Kim ◽  
Sung Park ◽  
Yong-Hoon Kim

In this paper, we demonstrate high-mobility inkjet-printed indium-gallium-zinc-oxide (IGZO) thin-film transistors (TFTs) using a solution-processed Sr-doped Al2O3 (SAO) gate dielectric. Particularly, to enhance to the electrical properties of inkjet-printed IGZO TFTs, a linear-type printing pattern was adopted for printing the IGZO channel layer. Compared to dot array printing patterns (4 × 4 and 5 × 5 dot arrays), the linear-type pattern resulted in the formation of a relatively thin and uniform IGZO channel layer. Also, to improve the subthreshold characteristics and low-voltage operation of the device, a high-k and thin (~10 nm) SAO film was used as the gate dielectric layer. Compared to the devices with SiO2 gate dielectric, the inkjet-printed IGZO TFTs with SAO gate dielectric exhibited substantially high field-effect mobility (30.7 cm2/Vs). Moreover, the subthreshold slope and total trap density of states were also significantly reduced to 0.14 V/decade and 8.4 × 1011/cm2·eV, respectively.


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