scholarly journals Privacy Protection in Real Time HEVC Standard Using Chaotic System

Cryptography ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 18
Author(s):  
Mohammed Abu Taha ◽  
Wassim Hamidouche ◽  
Naty Sidaty ◽  
Marko Viitanen ◽  
Jarno Vanne ◽  
...  
Keyword(s):  
Real Time ◽  
Reference Frames ◽  
High Efficiency ◽  
Video Frame ◽  
Selective Encryption ◽  
Compressed Video ◽  
Secret Key ◽  
High Efficiency Video Coding ◽  
Pull Out ◽  
Bit Stream

Video protection and access control have gathered steam over recent years. However, the most common methods encrypt the whole video bit stream as unique data without taking into account the structure of the compressed video. These full encryption solutions are time and power consuming and, thus, are not aligned with the real-time applications. In this paper, we propose a Selective Encryption (SE) solution for Region of Interest (ROI) security based on the tile concept in High Efficiency Video Coding (HEVC) standards and selective encryption of all sensitive parts in videos. The SE solution depends on a chaos-based stream cipher that encrypts a set of HEVC syntax elements normatively, that is, the bit stream can be decoded with a standard HEVC decoder, and a secret key is only required for ROI decryption. The proposed ROI encryption solution relies on the independent tile concept in HEVC that splits the video frame into independent rectangular areas. Tiles are used to pull out the ROI from the background and only the tiles figuring the ROI are encrypted. In inter coding, the independence of tiles is guaranteed by limiting the motion vectors of non-ROI to use only the unencrypted tiles in the reference frames. Experimental results have shown that the encryption solution performs secure video encryption in a real time context, with a diminutive bit rate and complexity overheads.

scholarly journals Robust and fast selective encryption for HEVC videos

2014 ◽  
Vol 10 (4) ◽  
pp. 221 ◽  
Author(s):  
Mokhtar Ouamri ◽  
Kamel M. Faraoun
Keyword(s):  
High Efficiency ◽  
Operating Mode ◽  
Advanced Encryption Standard ◽  
Selective Encryption ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Network Applications ◽  
Encryption Schemes ◽  
Visual Degradation ◽  
Reliability And Robustness

Emerging High efficiency video coding (HEVC) is expected to be widely adopted in network applications for high definition devices and mobile terminals. Thus, construction of HEVC's encryption schemes that maintain format compliance and bit rate of encrypted bitstream becomes an active security's researches area. This paper presents a novel selective encryption technique for HEVC videos, based on enciphering the bins of selected Golomb–Rice code’s suffixes with the Advanced Encryption Standard (AES) in a CBC operating mode. The scheme preserves format compliance and size of the encrypted HEVC bitstream, and provides high visual degradation with optimized encryption space defined by selected Golomb–Rice suffixes. Experimental results show reliability and robustness of the proposed technique.

scholarly journals Low delay error resilience algorithm for H.265|HEVC video transmission

2019 ◽  
Vol 17 (6) ◽  
pp. 2047-2063
Author(s):  
Taha T. Alfaqheri ◽  
Abdul Hamid Sadka
Keyword(s):  
Video Coding ◽  
Video Transmission ◽  
High Efficiency ◽  
Video Quality ◽  
Error Resilience ◽  
Video Codec ◽  
Compressed Video ◽  
High Efficiency Video Coding ◽  
Low Delay ◽  
The Impact

AbstractTransmission of high-resolution compressed video on unreliable transmission channels with time-varying characteristics such as wireless channels can adversely affect the decoded visual quality at the decoder side. This task becomes more challenging when the video codec computational complexity is an essential factor for low delay video transmission. High-efficiency video coding (H.265|HEVC) standard is the most recent video coding standard produced by ITU-T and ISO/IEC organisations. In this paper, a robust error resilience algorithm is proposed to reduce the impact of erroneous H.265|HEVC bitstream on the perceptual video quality at the decoder side. The proposed work takes into consideration the compatibility of the algorithm implementations with and without feedback channel update. The proposed work identifies and locates the frame’s most sensitive areas to errors and encodes them in intra mode. The intra-refresh map is generated at the encoder by utilising a grey projection method. The conducted experimental work includes testing the codec performance with the proposed work in error-free and error-prone conditions. The simulation results demonstrate that the proposed algorithm works effectively at high packet loss rates. These results come at the cost of a slight increase in the encoding bit rate overhead and computational processing time compared with the default HEVC HM16 reference software.

scholarly journals Scalable FPGA Hardware Acceleration for H.264 Motion Estimation

2021 ◽  
Author(s):  
Theepan Moorthy
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Video Compression ◽  
Reference Frames ◽  
Hardware Acceleration ◽  
Compressed Video ◽  
Time Performance ◽  
Wide Range ◽  
Multiple Reference Frames ◽  
Multiple Reference

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

A selective encryption scheme of CABAC based on video context in high efficiency video coding

2017 ◽  
Vol 77 (10) ◽  
pp. 12837-12851 ◽  
Author(s):  
Jianjun Li ◽  
Chenyan Wang ◽  
Xie Chen ◽  
Zheng Tang ◽  
Guobao Hui ◽  
...  
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Encryption Scheme ◽  
Selective Encryption ◽  
High Efficiency Video Coding

scholarly journals Scalable FPGA Hardware Acceleration for H.264 Motion Estimation

2021 ◽  
Author(s):  
Theepan Moorthy
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Video Compression ◽  
Reference Frames ◽  
Hardware Acceleration ◽  
Compressed Video ◽  
Time Performance ◽  
Wide Range ◽  
Multiple Reference Frames ◽  
Multiple Reference

The H.264 video compression standard uses enhanced Motion Estimation (ME) features to improve both the compression ratio and the quality of compressed video. The two primary enhancements are the use of Variable Block Size Motion Estimation (VBSME) and multiple reference frames. These two additions greatly increase the computational complexity of the ME algorithm, to the point where a software based real-time (30 frames per second (fps)) implementation is not possible on present microprocessors. Thus hardware acceleration of the H.264 ME algorithm is necessary in order to achieve real-time performance for the implementation of the VBSME and multiple reference frames features. This thesis presents a scalable FPGA-based ME architecture that supports real-time H.264 ME for a wide range of video resolutions ─ from 640x480 VGA to 1920x1088 High Definition (HD). The architecture contains innovations in both the data-path design and memory organization to achieve scalability and real-time performance on FPGAs. At 37% FPGA device utilization, the architecture is able to achieve 31 fps performance for encoding full 1920x1088 progressive HDTV video.

scholarly journals FPGA-based implementation of intra prediction module for HEVC decoder

2019 ◽  
Vol 8 (2) ◽  
pp. 6130-6137
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Cmos Technology ◽  
Intra Prediction ◽  
Hardware Architecture ◽  
Video Frame ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Prediction Module ◽  
Block Sizes

The High Efficiency Video Coding (HEVC) is the new standard which is designed to support High Definition (HD) and Ultra-HD video cotenants. In HEVC, several new coding tools are adopted in order to improve the coding efficiency and compression ratio but with a significant increase in the computational complexity comparing to the previous standard H.264/AVC. In this paper, we focus on reducing the complexity of the most consuming block in the HEVC decoder standard which is the intra prediction module. In this context, we propose an optimized hardware architecture dedicated to support the 34 modes of intra prediction module considering 4×4, 8×8 and 16×16 block sizes. The proposed design exploits the symmetric property between horizontal and vertical modes. Hence, we implement a new hardware architecture that factorizes the same hardware resources for both directions which leads to save the hardware cost, the power consumption and the processing time. Furthermore, the different block sizes are implemented independently in order to avoid memory overhead while accessing to the shared memory. The implemented design using Xilinx Zynq-based FPGA platform can process in real time the Ultra-HD video frame of resolution (4096×2048) at 232 MHz. As well, the synthesis results using the TSMC 180 nm CMOS technology provide similar performance than our FPGA implementation. Finally, the HW/SW implementation of full HEVC decoder can process the decoding of 15 FPS in best case for 240p video resolution with a gain of 60% in power consumption.

scholarly journals Block Based Enhancement using Deep Learning for Conversion of Low Resolution AVS Video to High Resolution HEVC Video

2021 ◽  
Author(s):  
Rizwan Qureshi ◽  
Mehmood Nawaz
Keyword(s):  
Deep Learning ◽  
High Efficiency ◽  
Motion Vector ◽  
Super Resolution ◽  
Computational Time ◽  
Video Frame ◽  
Low Resolution ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Resolution Method

Conversion of one video bitstream to another video bitstream is a challenging task in the heterogeneous transcoder due to different video formats. In this paper, a region of interest (ROI) based super resolution technique is used to convert the lowresolution AVS (audio video standard) video to high definition HEVC (high efficiency video coding) video. Firstly, we classify a low-resolution video frame into small blocks by using visual characteristics, transform coefficients, and motion vector (MV) of a video. These blocks are further classified as blocks of most interest (BOMI), blocks of less interest (BOLI) and blocks of noninterest (BONI). The BONI blocks are considered as background blocks due to less interest in video and remains unchanged during SR process. Secondly, we apply deep learning based super resolution method on low resolution BOMI, and BOLI blocks to enhance the visual quality. The BOMI and BOLI blocks have high attention due to ROI that include some motion and contrast of the objects. The proposed method saves 20% to 30% computational time and obtained appreciable results as compared with full frame based super resolution method. We have tested our method on different official video sequences with resolution of 1K, 2K, and 4K. Our proposed method has an efficient visual performance in contrast to the full frame-based super resolution method.

Sign in / Sign up

Export Citation Format

Share Document